Non-volatile push-pull non-volatile memory cell having reduced operation disturb and process for manufacturing same
A non-volatile memory cell includes a p-channel non-volatile transistor having a source and a drain defining a channel and a gate overlying the channel and an n-channel non-volatile transistor having a source and a drain defining a channel and a gate overlying the channel. In at least one of the p-channel non-volatile transistor and the n-channel non-volatile transistor, a lightly-doped drain region extends from the drain into the channel.
1. A non-volatile memory cell, comprising:
a p-channel non-volatile transistor having a source and a drain defining a channel and a gate overlying the channel;
an n-channel non-volatile transistor having a source and a drain defining a channel and a gate overlying the channel, the drain of the p-channel non-volatile transistor connected to the drain of the n-channel non-volatile transistor; and
in at least one of the p-channel non-volatile transistor and the n-channel non-volatile transistor, a lightly-doped drain region extending from the drain towards the channel, and a lightly-doped drain region extending from the source towards the channel, the lightly-doped drain region extending from the source having a higher doping level than the lightly-doped drain region extending from the drain.
2. The non-volatile memory cell of claim 1 further including a volatile switch transistor having a gate connected to the drains of the p-channel non-volatile transistor and the n-channel non-volatile transistor.
3. The non-volatile memory cell of claim 1 wherein lightly-doped drain regions extend from the drain of the p-channel non-volatile transistor towards the channel of the p-channel non-volatile transistor and from the source of the p-channel non-volatile transistor towards the channel of the p-channel non-volatile transistor.
4. The non-volatile memory cell of claim 1 wherein lightly-doped drain regions extend from the drain of the n-channel non-volatile transistor towards the channel of the n-channel non-volatile transistor and from the source of the n-channel non-volatile transistor towards the channel of the n-channel non-volatile transistor.
5. A non-volatile memory cell, comprising:
a p-channel non-volatile transistor having a source and a drain defining a channel, a gate overlying the channel, a lightly-doped drain region extending from the drain towards the channel, and a lightly-doped drain region extending from the source towards the channel;
an n-channel non-volatile transistor having a source and a drain defining a channel and a gate overlying the channel; and
wherein the lightly-doped drain region extending from the source of the p-channel non-volatile transistor has a higher doping level than the lightly-doped drain region extending from the drain of the p-channel non-volatile transistor.
6. The non-volatile memory cell of claim 5 further including a volatile switch transistor having a gate connected to the drains of the p-channel non-volatile transistor and the n-channel non-volatile transistor.
7. A non-volatile memory cell, comprising:
a p-channel non-volatile transistor having a source and a drain defining a channel, a gate overlying the channel, a lightly-doped drain region extending from the drain towards the channel, and a lightly-doped drain region extending from the source towards the channel;
an n-channel non-volatile transistor having a source and a drain defining a channel, a gate overlying the channel, a lightly-doped drain region extending from the drain towards the channel, and a lightly-doped drain region extending from the source towards the channel;
wherein the lightly-doped drain region extending from the source of the p-channel non-volatile transistor has a higher doping level than the lightly-doped drain region extending from the drain of the p-channel non-volatile transistor; and
wherein the lightly-doped drain region extending from the source of the n-channel non-volatile transistor has a higher doping level than the lightly-doped drain region extending from the drain of the n-channel non-volatile transistor.
8. The non-volatile memory cell of claim 7 further including a volatile switch transistor having a gate connected to the drains of the p-channel non-volatile transistor and the n-channel non-volatile transistor.