Silicon carbide vertical-sidewall dual-mesa static induction transistor
View Patent ↗A vertical-sidewall dual-mesa static induction transistor (SIT) structure includes a silicon carbide substrate having a layer arrangement formed thereon. Laterally spaced ion implanted gate regions are defined in the layer arrangement. Source regions are defined in the layer arrangement. Each of the source regions can include a channel mesa having a source mesa disposed thereon. The source mesa includes upright sidewalls relative to a principal plane of the substrate defining a horizontal dimension thereof. The channel mesa includes upright sidewalls relative to the source mesa and the principal plane of the substrate. Also disclosed is a method of fabricating a vertical-sidewall dual-mesa SiC transistor device. The method includes implanting ions at an angle relative to a principal plane of the substrate to form gate junctions in upper portions of the substrate and lateral portions of the upright channel mesas.
1. A static induction transistor structure, comprising:
a silicon carbide substrate having a layer arrangement formed thereon;
a plurality of laterally spaced ion implanted gate regions defined in the layer arrangement; and
a plurality of source regions defined in the layer arrangement, each of the plurality of source regions being positioned adjacent to respective ones of the gate regions,
wherein:
each of the source regions includes a first mesa having a second mesa disposed thereon;
the second mesa includes upright sidewalls relative to a principal plane of the substrate, the principal plane of the substrate defining a horizontal dimension thereof; and
the first mesa includes upright sidewalls relative to the principal plane of the substrate.
2. The static induction transistor structure of claim 1 , wherein at least one of the plurality of source regions further includes a channel having a substantially constant width (W) relative to the upright sidewalls.
3. The static induction transistor structure of claim 1 , wherein the second mesa for each source region is a source mesa coupled to a source contact.
4. The static induction transistor structure of claim 1 , wherein the second mesa includes sidewalls that are recessed laterally relative to sidewalls of the first mesa.
5. The static induction transistor structure of claim 3 , wherein each of the plurality of source regions is communicatively coupled to a source bus through each source mesa.
6. The static induction transistor structure of claim 1 , further comprising a source ohmic contact coupled to the second mesa.
7. The static induction transistor structure of claim 6 , further comprising a source bus coupled to the second mesa via the source ohmic contact.
8. The static induction transistor structure of claim 7 , further comprising an interlayer dielectric film disposed on a passivation film and between the source bus and the plurality of gate regions.
9. The static induction transistor structure of claim 7 , further comprising a source bond pad formed on the source bus.
10. The static induction transistor structure of claim 9 , further comprising a passivation layer on the source bond pad, wherein the passivation layer includes one or more bond pad openings formed therein.
11. The static induction transistor structure of claim 1 , further comprising ohmic contacts coupled to a bottom surface of the substrate, and a backside metal coupled to the ohmic contacts.
12. A dual-mesa static induction transistor device, comprising:
a silicon carbide substrate;
first and second trenches defined in the substrate;
a channel mesa disposed between the first and second trenches, the channel mesa having upright sidewalls defining a rectangular cross section thereof;
a source mesa atop the channel mesa, the source mesa having sidewalls recessed laterally relative to the sidewalls of the channel mesa; and
an ion implanted doped region extending into the channel mesa through the upright sidewalls so as to define a substantially rectangular channel between the sidewalls of the channel mesa.