RAM block designed for efficient ganging
View Patent ↗A random-access memory block for a field programmable gate array includes a random-access memory array having address inputs, a data input, a data output and including a plurality of storage locations. At least two programmably invertible enable inputs are provided. Hardwired decoding logic is coupled to the at least two programmably invertible enable inputs to selectively enable the random-access memory array. A gate is coupled to the output of the random-access memory array and is configured to pass the output of the random-access memory array only if the random-access memory is enabled for a read operation, and otherwise generate a preselected logic state.
1. In a field-programmable gate array, a random-access memory block comprising:
a random-access memory array having address inputs, a data input, a data output and including a plurality of storage locations;
at least two programmably invertible block-enable inputs;
hardwired decoding logic having inputs coupled to the at least two programmably invertible block-enable inputs to selectively enable the random-access memory array by generating a block-enable signal at an output in response to a preselected combination of data signals presented to the at least two programmably invertible block-enable inputs;
a gate having a first input coupled to the data output of the random-access memory array and a second input coupled to the output of the hardwired decoding logic and configured to pass the output of the random-access memory array only if the block-enable signal is present on the second input and if the random-access memory is enabled for a read operation, and otherwise generate a preselected logic state.
2. The random-access memory block of claim 1 , further including:
a multiplexer having a first data input coupled to the output of the gate, a second data input coupled to the output of the random-access memory array; and
a select input.
3. The random-access memory block of claim 2 wherein the select input of the multiplexer is coupled to a programmable bit.
4. The random-access memory block of claim 3 wherein the select input of the multiplexer is coupled to a mode control signal.
5. In a field-programmable gate array, a random-access memory block comprising:
a random-access memory array having address inputs, a data input, a data output and including a plurality of storage locations;
at least two programmably invertible enable inputs, each coupled to a different one of a plurality of memory address lines;
hardwired decoding logic coupled to the at least two programmably invertible enable inputs, the decoding logic having an output;
a block-enable register coupled to the output of the decoding logic;
a write enable register;
a data-input register coupled to the data input of the random-access memory array;
a memory address register having inputs coupled to an address bus and outputs coupled to the address inputs of the random-access memory array; and
a gate having a first input coupled to the output of the block-enable register, a second input coupled to the output of the write-enable register and a third input coupled to the output of the random-access memory array, and an output, the gate configured to pass to its output the output of the random-access memory array only if the contents of the block-enable register are true and the write-enable register indicates a read operation.
6. The random-access memory block of claim 5 wherein the decoding logic is an AND gate.
7. The random-access memory block of claim 5 wherein the gate is an OR gate.
8. The random-access memory block of claim 5 wherein the data output is coupled to an OR gate.
9. A method for operating a random-access memory block in a field-programmable gate array comprising:
enabling the random-access memory block only when it is uniquely selected by a block-enable signal, generated from decoding logic coupled to at least two programmably invertible block-enable inputs, and a read operation is requested by a read-enable signal separate from the block-enable signal; and
generating output data at an output of the random-access memory block when it is uniquely selected by the block-enable signal and a read operation is requested by the read-enable signal, otherwise generating a preselected logic state at the output of the random-access memory block.
10. The method of claim 9 wherein generating a preselected logic state at the output of the random-access memory block comprises generating a logic zero.
11. In a field-programmable gate array, a group of random-access memory blocks comprising:
a plurality of random-access memory blocks, each random-access memory block including:
a random-access memory array having address inputs, a data input, a data output and including a plurality of storage locations;
at least two programmably invertible block-enable inputs;
hardwired decoding logic having inputs coupled to the at least two programmably invertible block-enable inputs to selectively enable the random-access memory array by generating a block-enable signal at an output in response to a preselected combination of data signals presented to the at least two programmably invertible block-enable inputs;
a gate having a first input coupled to the data output of the random-access memory array and a second input coupled to the output of the hardwired decoding logic and configured to pass the output of the random-access memory array only if the block-enable signal is present on the second input and if the random-access memory is enabled for a read operation, and otherwise generate a preselected logic state;
a combining gate having a plurality of inputs and an output, each of the plurality of inputs coupled to the data output of a different one of the plurality of random-access memory blocks, the output of the gate forming an output of the group of random-access memory blocks.
12. In a field-programmable gate array, a random-access memory block comprising:
a random-access memory array having address inputs, a data input, a data output and including a plurality of storage locations;
at least one of a read-enable input and a write-enable input;
at least two programmably invertible block-enable inputs;
decoding logic coupled to the at least two programmably invertible block-enable inputs to selectively enable the random-access memory array block; and
wherein the output of the random-access memory array block is driven when the random-access memory block is enabled and when the random-access memory block is not enabled.
13. In a field-programmable gate array, a random-access memory block comprising:
a random-access memory array having address inputs, a data input, a data output and including a plurality of storage locations;
at least one of a read-enable input and a write-enable input;
at least one block-enable input;
a gate coupled to the output of the random-access memory array and configured to pass the output of the random-access memory array only if a block-enable signal from the block-enable input indicates that the random-access memory block has been selected and if the random-access memory array is enabled for a read operation, and otherwise generate a preselected logic state.