IP Library Granted Patent US 7,192,837
Granted Patent B2
US 7,192,837 · App. 10/765,027 · Granted Mar 20, 2007

Methods of manufacturing MOSFET devices

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,192,837
App. No.
10/765,027
Granted
Mar 20, 2007
Kind
B2
Abstract

Example methods of manufacturing MOSFET devices are disclosed. One example method may include an oxidation, an etching, an ion implanting for a threshold voltage control to form an elevated source/drain region and thereby implements an ultra shallow junction.

Claims (38)

1. A method for manufacturing a MOSFET device, the method comprising:

forming a shallow trench isolation in a substrate;

farming a first oxide layer on a surface of an active region of the substrate and implanting ions thereinto for forming a lightly doped drain in the active region prior to the formation of a gate;

forming a first nitride layer;

removing a part of the first nitride layer and the first oxide layer and etching the substrate corresponding to the part, including the tightly doped drain, by a depth of about 200 to about 1000 angstroms to define a gate region;

forming a second oxide layer aver an exposed portion of the substrate;

implanting ions into the substrate;

removing the second oxide layer;

depositing a gate insulating layer and a polysilicon layer into the removed parts of the first nitride layer and the first aid do layer;

polishing until the first nitride layer is exposed;

removing the first nitride layer, depositing an oxide layer conformally and depositing a second nitride layer;

etching the second nitride layer to form a gate sidewall;

implanting ions into the substrate to form a source and drain at locations which are deeper than that of the lightly doped drain and at sides of the gate; and

removing an exposed oxide layer.

2. A method as defined by claim 1 , wherein the substrate comprises a silicon substrate.

3. A method as defined by claim 1 , wherein the shallow trench isolation comprises an oxide layer.

4. A method as defined by claim 1 , wherein forming the second oxide layer comprises oxidizing the exposed substrate at a temperature of from about 600 to about 800° C., such that the second oxide layer has a thickness of about 100 angstroms.

5. A method as defined by claim 1 , wherein the polishing comprises chemical mechanical polishing.

6. A method as defined by claim 1 , wherein removing the second nitride layer comprises etch back processing.

7. A method for manufacturing a MOSFET device, the method comprising:

implanting ions into an active region of a substrate to form a lightly doped drain (LDD) prior to forming a gate;

forming a first nitride layer on the substrate, including the active region;

removing a part of the first nitride layer and etching to exposed substrate, including the LDD, to a predetermined depth to define a gate region;

implanting ions into the substrate to control a voltage threshold of the MOSFET device;

forming a gate insulating layer and a polysilicon layer in the gate region;

removing to first nitride layer, then depositing an oxide layer and a second nitride layer on to polysilicon layer;

etching the second nitride layer to form a gate sidewall; and

implanting ions into the substrate to form a source and drain at locations which are deeper than that of the LDD and at sides of the gate.

8. A method as defined by claim 7 , wherein the substrate comprises a silicon substrate.

9. A method as defined by claim 7 , further comprising forming a shallow trench isolation in the substrate to define the active region prior to implanting ions to form a LDD.

10. A method as defined by claim 9 , wherein the shallow trench isolation comprises an oxide layer.

11. A method as defined by claim 7 , wherein forming the polysilicon layer comprises depositing polysilicon onto the gate insulating layer in the gate region and chemical mechanical polishing the polysilicon.

12. A method as defined by claim 11 , wherein forming the gate insulating layer comprises depositing the gate insulating layer in the gate region.

13. A method as defined by claim 7 , wherein removing the second nitride layer comprises etch back processing.

14. A method as defined by claim 7 , wherein the predetermined depth is from about 200 to about 1000 angstroms.

15. A method as defined by claim 7 , further comprising, prior to implanting ions into the substrate to control the voltage threshold of the MOSFET device, forming a second oxide layer over an exposed portion of the substrate.

16. A method as defined by claim 15 , further comprising, after implanting ions into the substrate to control the voltage threshold or the MOSFET device, removing the second oxide layer.

17. A method as defined by claim 7 , further comprising, after implanting ions into the substrate to form the source and drain, removing an exposed oxide layer.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR PREVIOUSLY RECORDED ON REEL 017703 FRAME 0499. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNOR SHOULD BE "DONGBUANAM SEMICONDUCTOR INC.". Recorded Jun 28, 2006
From: DONGBUANAM SEMICONDUCTOR INC.
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 017854/0297 →
CHANGE OF NAME Recorded May 30, 2006
From: DONGANAM SEMICONDUCTOR INC.
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 017703/0499 →
MERGER Recorded May 31, 2005
From: ANAM SEMICONDUCTOR INC.; ANAM SEMICONDUCTOR INC.
To: DONGBUANAM SEMICONDUCTOR, INC., A KOREAN CORPORATION
Reel/Frame 016593/0917 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 13, 2004
From: KOH, KWAN JU
To: ANAM SEMICONDUCTOR, INC.
Reel/Frame 014975/0566 →