Integrated test circuit, a test circuit, and a test method for performing transmission and reception processing to and from a first and a second macro block at a first frequency
View Patent ↗A macro block MB 2 including a physical-layer circuit PHY for communications performs transmission and reception processing to and from a macro block MB 1 at a clock frequency CF 1 . A test circuit TC includes a test transmission buffer TXB that stores a transmission data signal from a test input terminal TPI at a frequency CF 2 that is lower than the frequency CF 1 , and a test reception buffer RXB that outputs a reception data signal to a test output terminal TPO at a frequency CF 3 that is lower than the frequency CF 1 . After the transmission buffer TXB has stored the transmission data signal from the terminal TPI at the frequency CF 2 , it outputs the stored transmission data signal to the MB 2 at the frequency CF 1 . After the reception buffer RXB has stored the reception data signal from the MB 2 at the frequency CF 1 , it outputs the stored reception data signal to the terminal TPO at the frequency CF 3.
1. A test circuit for a second macro block that performs transmission and reception processing to and from a first macro block at a first clock frequency, the test circuit comprising:
a test transmission buffer which stores a transmission data signal from a test input terminal at a second clock frequency that is lower than the first clock frequency; and
a test reception buffer which outputs a reception data signal from the second macro block to a test output terminal at a third clock frequency that is lower than the first clock frequency,
wherein, after storing the transmission data signal from the test input terminal at the second clock frequency, the test transmission buffer outputs the stored transmission data signal to the second macro block at the first clock frequency, the second macro block including a physical-layer circuit for data communications, and
wherein, after storing the reception data signal from the second macro block at the first clock frequency, the test reception buffer outputs the stored reception data signal to the test output terminal at the third clock frequency.
2. The test circuit as defined in claim 1 ,
wherein, when the second macro block that has received the transmission data signal performs transmission and reception processing in a loopback mode over a first bus that differs from a bus between the first and second macro blocks, and has output the reception data signal received in loopback mode to the first macro block side at the first clock frequency,
the test reception buffer stores the reception data signal from the second macro block at the first clock frequency and outputs the stored reception data signal to the test output terminal at the third clock frequency.
3. The test circuit as defined in claim 1 , further comprising:
a communications sequencer for performing transmission and reception processing to and from the second macro block by a predetermined communications protocol,
wherein the communications sequencer performs processing for transmitting the transmission data signal stored in the test transmission buffer to the second macro block at the first clock frequency, and performs processing for receiving the reception data signal from the second macro block into the test reception buffer at the first clock frequency.
4. An integrated circuit comprising a test circuit for a second macro block that performs transmission and reception processing to and from a first macro block at a first clock frequency, the test circuit comprising:
a first macro block;
a second macro block;
a test transmission buffer which stores a transmission data signal from a test input terminal at a third clock frequency that is lower than the first clock frequency;
a test reception buffer which outputs a reception data signal from the second macro block to a test output terminal at a third clock frequency that is lower than the first clock frequency;
wherein, after storing the transmission data signal from the test input terminal at the second clock frequency, the test transmission buffer outputs the stored transmission data signal to the second macro block at the first clock frequency, the second macro block including a physical-layer circuit for data communications, and
wherein, after storing the reception data signal from the second macro block at the first clock frequency, the test reception buffer outputs the stored reception data signal to the test output terminal at the third clock frequency.
5. An integrated circuit comprising:
the test circuit as defined in claim 4 ;
wherein, when the second macro block that has received the transmission data signal performs transmission and reception processing in a loopback mode over a first bus that differs from a bus between the first and second macro blocks, and has output the reception data signal received in loopback mode to the first macro block side at the first clock frequency,
the test reception buffer stores the reception data signal from the second macro block at the first clock frequency and outputs the stored reception data signal to the test output terminal at the third clock frequency.
6. An integrated circuit comprising:
the test circuit as defined in claim 4 ;
a communications sequencer for performing transmission and reception processing to and from the second macro block by a predetermined communications protocol,
wherein the communications sequencer performs processing for transmitting the transmission data signal stored in the test transmission buffer to the second macro block at the first clock frequency, and performs processing for receiving the reception data signal from the second macro block into the test reception buffer at the first clock frequency;
the first macro block; and
the second macro block.
7. A test method for testing for a second macro block which performs transmission and reception processing to and from a first macro block at a first clock frequency, using a test circuit including a test transmission buffer and a test reception buffer, the test method comprising:
storing a transmission data signal from a test input terminal into the test transmission buffer at a second clock frequency that is lower than the first clock frequency and, after the transmission data signal has been stored, outputting the stored transmission data signal to the second macro block at the first clock frequency, the second macro block including a physical-layer circuit for data communications; and
storing a reception data signal from the second macro block into the test reception buffer at the first clock frequency and, after the reception data signal has been stored, outputting the stored reception data signal to the test output terminal at a third clock frequency that is lower than the first clock frequency.
8. The test method as defined in claim 7 ,
wherein, when the second macro block that has received the transmission data signal performs transmission and reception processing in loopback mode and has output the reception data signal received in loopback mode at the first clock frequency, the output reception data signal is stored in the test reception buffer at the first clock frequency and the stored reception data signal is output to the test output terminal at the third clock frequency.
9. The test method as defined in claim 7 ,
wherein the test circuit comprises a communications sequencer for performing transmission and reception processing to and from the second macro block by a predetermined communications protocol,
wherein the communications sequencer is used for transmitting the transmission data signal, which has been stored in the test transmission buffer, to the second macro block at the first clock frequency, and
wherein the communications sequencer is used for receiving the reception data signal from the second macro block into the test reception buffer at the first clock frequency.