IP Library Granted Patent US 7,049,677
Granted Patent B2
US 7,049,677 · App. 10/767,384 · Granted May 23, 2006

Low cost dielectric isolation method for integration of vertical power MOSFET and lateral driver devices

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Quick Facts
Patent No.
US 7,049,677
App. No.
10/767,384
Granted
May 23, 2006
Kind
B2
Abstract

A semiconductor device has a driver device ( 10 ) in proximity to a power device ( 12 ). In making the semiconductor device, an N+ layer ( 24 ) is formed on a substrate ( 22 ). A portion of the N+ layer is removed, substantially down to the substrate, to provide a layer offset ( 28 ) between the driver device area and power device area. An epi region of uniform thickness is formed over the driver device and power device areas. A portion of the epi layer is removed to provide another layer offset ( 70 ). An oxide layer ( 68 ) of uniform thickness is formed over the epi region. The oxide layer is planarized to remove oxide layer over the N+ layer. An oxide-filled trench ( 80 ) is formed between the driver device and the power device. The oxide-filled trench extends down to the oxide layer to isolate the driver device from the power device.

Claims (67)

1. A method of forming a semiconductor device, comprising:

providing a substrate;

forming a first layer of semiconductor material over the substrate;

removing a portion of the first layer to provide a layer offset between a removed portion of the first layer and a remaining portion of the first layer;

forming an oxide layer of uniform thickness over the removed portion of the first layer and the remaining portion of the first layer;

planarizing the oxide layer so that the oxide layer over the remaining portion of the first layer is removed;

forming a polysilicon region over the planarized oxide layer;

forming an epi region over the remaining portion of the first layer;

forming a trench between the polysilicon region and. the api region extending vertically down to the oxide layer; and

depositing oxide in the trench down to the oxide layer to isolate the polysilicon region.

2. The method of claim 1 , wherein the substrate is N-type semiconductor material.

3. The method of claim 1 , wherein the first layer of semiconductor material receives N-type dopants.

4. The method of claim 1 , wherein the step of removing a portion of the first layer includes the step of removing the first layer substantially down to the substrate.

5. The method of claim 1 , further including the steps of:

forming a first well in the polysilicon region;

forming a second well in the first well;

forming a first transistor in the first well; and

forming a second transistor in the second well.

6. The method of claim 5 , further including the steps of: forming a third well in the epi region; and

forming a power transistor in the third well.

7. A method of forming an integrated circuit having a driver device in proximity to a power device, comprising:

forming an oxide layer below the driver device;

forming a trench between the driver device and the power device, wherein the trench extends down to the oxide layer;

depositing oxide in the trench down to the oxide layer to isolate the driver device from the power device;

providing a substrate;

forming a first layer of semiconductor material over the substrate;

removing a portion of the first layer to provide a layer offset between a removed portion of the first layer and a remaining portion of the first layer; and

forming the oxide layer having uniform thickness over the removed portion of the first layer and the remaining portion of the first layer.

8. The method of claim 7 , further including the steps of:

planarizing the oxide layer so that the oxide layer over the remaining portion of the first layer is removed;

forming a polysilicon region over the planarized oxide layer;

forming an epi region over the remaining portion of the first layer; and

forming the trench between the polysilicon region and the epi region egtending vertically down to the oxide layer.

9. The method of claim 8 , wherein the first layer of semiconductor material is an extension layer of the substrate.

10. The method of claim 8 , wherein the first layer of semiconductor material is an epi layer.

11. The method of claim 8 , further including the steps of:

forming a first well in the polysilicon region;

forming a second well in the first well;

forming a first transistor in the first well; and

forming a second transistor in the second well.

12. The method of claim 11 , further including the steps of: forming a third well in the epi region; and forming a power transistor in the well.

13. A semiconductor device having a driver device in proximity to a power device, the semiconductor device being made by the process comprising the steps of:

forming an oxide layer below the driver device;

forming a trench between the driver device and the power device, wherein the trench extends down to the oxide layer;

depositing oxide in the trench down to the oxide layer to isolate the driver device from the power device;

providing a substrate;

forming a first layer of semiconductor material over the substrate;

removing a portion of the first layer to provide a layer offset between a removed portion of the first layer and a remaining portion of the first layer; and

forming the oxide layer having uniform thickness over the removed portion of the first layer and the remaining portion of the first layer.

14. The semiconductor device of claim 13 , wherein the process further includes the steps of:

planarizing the oxide layer so that the oxide layer over the remaining portion of the first layer is removed;

forming a polysilicon region over the planarized oxide layer;

forming an epi region over the remaining portion of the first layer; and

forming the trench between the polysilicon region and the epi region extending vertically down to the oxide layer.

15. A method of forming a first semiconductor device in proximity to a second semiconductor device on an integrated circuit, comprising:

forming an oxide layer below the first semiconductor device;

forming a trench between the first and second semiconductor devices, wherein the trench extends down to the oxide layer;

depositing oxide in the trench down to the oxide layer to isolate the first and second semiconductor devices;

providing a substrate;

forming a first layer of semiconductor material over the substrate;

removing a portion of the first layer to provide a layer offset between a removed portion of the first layer and a remaining portion of the first layer; and

forming the oxide layer having uniform thickness over the removed portion of the first layer and the remaining portion of the first layer.

16. The method of claim 15 , further including the steps of:

planarizing the oxide layer so that the oxide layer over the remaining portion of the first layer is removed;

forming a polysilicon region over the planarized oxide layer;

forming an epi region over the remaining portion of the first layer; and

forming the trench between the polysilicon region and the epi region extending vertically down to the oxide layer.

Assignments (12)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 5, 2017
From: PAI CAPITAL LLC
To: BEL POWER SOLUTIONS INC.
Reel/Frame 043086/0433 →
NUNC PRO TUNC ASSIGNMENT Recorded Jun 25, 2014
From: POWER-ONE, INC.
To: PAI CAPITAL LLC
Reel/Frame 033227/0968 →
RELEASE OF SECURITY INTEREST Recorded May 5, 2014
From: BANK OF AMERICA, N.A. AS ADMINISTRATIVE AGENT
To: POWER-ONE, INC.
Reel/Frame 032826/0684 →
SECURITY AGREEMENT Recorded Jun 7, 2011
From: POWER-ONE, INC.
To: BANK OF AMERICA, N.A.
Reel/Frame 026401/0098 →
RELEASE OF SECURITY INTEREST Recorded Mar 26, 2011
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A. (AS SUCCESSOR TO THE BANK OF NEW YORK TRUST COMPANY, N.A.)
To: POWER-ONE, INC.
Reel/Frame 026026/0794 →
SECURITY AGREEMENT Recorded Jul 17, 2008
From: POWER-ONE, INC.
To: THE BANK OF NEW YORK TRUST COMPANY, N.A.
Reel/Frame 021253/0076 →
RELEASE OF SECURITY INTEREST Recorded Jul 17, 2008
From: PWER BRIDGE, LLC
To: POWER-ONE, INC.
Reel/Frame 021253/0024 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE ADDR Recorded Mar 20, 2008
From: POWER-ONE, INC.
To: PWER BRIDGE, LLC
Reel/Frame 020741/0403 →
SECURITY AGREEMENT Recorded Mar 7, 2008
From: POWER-ONE, INC.
To: PWER BRIDGE, LLC
Reel/Frame 020617/0177 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 31, 2005
From: POWER-ONE LIMITED
To: POWER-ONE, INC.
Reel/Frame 017212/0054 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 12, 2005
From: POWER-ONE LIMITED
To: POWER-ONE, INC.
Reel/Frame 016768/0399 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 28, 2004
From: FATEMIZADEH, BADREDIN; SALIH, ALI
To: POWER-ONE LIMITED
Reel/Frame 014948/0671 →