Integrated circuit devices having contact holes exposing gate electrodes in active regions
Integrated circuit devices are provided including an integrated circuit substrate and first, second and third spaced apart insulating regions in the integrated circuit substrate that define first and second active regions. A first gate electrode is provided on the first active region. The first gate electrode has a first portion on the first active region that extends onto the first insulating region and a second portion at an end of the first portion on the first insulating region. A second gate electrode is provided on the second active region. An insulating layer is provided on the first, second and third active regions defining a first gate contact hole that exposes at least a portion of the second portion of the first gate electrode. The first gate electrode is free of a gate contact hole on the first portion of the first gate electrode. A second gate contact hole is provided on the second active region that exposes at least a portion of the second gate electrode. Related methods of fabricating integrated circuit devices are also provided.
1. An integrated circuit device comprising:
an integrated circuit substrate;
first, second and third spaced apart insulating regions in the integrated circuit substrate that define first and second active regions;
a first gate electrode on the first active region, the first gate electrode having a first portion on the first active region that extends onto the first insulating region and a second portion at an end of the first portion on the first insulating region;
a second gate electrode on the second active region; and
an insulating layer on the first, second and third insulating regions defining a first gate contact hole that exposes at least a portion of the second portion of the first gate electrode, the first gate electrode being free of a gate contact hole on the first portion, and a second gate contact hole on the second active region that exposes at least a portion of the second gate electrode;
wherein the second gate electrode comprises a first portion on the second active region that extends on the third insulating region and a second portion at an end of the first portion on the third insulating region and wherein the second gate contact hole exposes at least a portion of the first portion of the second gate electrode, wherein the insulating layer further defines a third gate contact hole, and wherein the third gate contact hole exposes at least a portion of the second portion of the second gate electrode.
2. The integrated circuit device of claim 1 wherein the insulating layer further defines a fourth gate contact hole, the fourth gate contact hole exposing at least of portion of the first portion of the second gate electrode.
3. The integrated circuit device of claim 1 further comprising:
a first gate interconnect that is electrically coupled to the second portion of the first gate electrode through the first gate contact hole; and
a second gate interconnect that is electrically coupled to the second gate electrode through the second gate contact hole.
4. An integrated circuit device comprising:
an integrated circuit substrate;
first, second and third spaced apart insulating regiong in the integrated circuit substrate that define first and second active regions;
a first gate electrode on the first active region, the first gate electrode having a first portion on the first active region that extends onto the first insulating region and a second portion at an end of the first portion on the first insulating region;
a second gate electrode on the second active region; and
an insulating layer on the first, second and third insulating regions defining a first gate contact hole that exposes at least a portion of the second portion of the first gate electrode, the first gate electrode being free of a gate contact hole on the first portion, and a second gate contact hole on the second active region that exposes at least a portion of the second gate electrode and wherein the first region of the integrated circuit substrate comprises a short channel MOS transistor region and the second region of the integrated circuit substrate comprises a long channel MOS transistor region, wherein the first gate electrode has a first width and the second gate electrode has a second width and wherein the second width of the second gate electrode is greater than the first width of the first gate electrode.
5. The integrated circuit device of claim 1 further comprising:
a first gate insulating layer between the first gate electrode and the first active region, the first gate insulating layer having a first thickness; and
a second gate insulating layer between the second gate electrode and the second active region, the second gate insulating layer having a second thickness, wherein the first region of the integrated circuit subsirate comprises a low voltage MOS transistor region and the second region of the integrated circuit substrate comprises a high voltage MOS transistor region, and wherein the second thickness of the second gate insulating layer is thicker than the first thickness of the first gate insulating layer.