IP Library Granted Patent US 6,982,663
Granted Patent B2
US 6,982,663 · App. 10/770,213 · Granted Jan 3, 2006

Method and system for symbol binarization

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Quick Facts
Patent No.
US 6,982,663
App. No.
10/770,213
Granted
Jan 3, 2006
Kind
B2
Abstract

The present invention is directed to an improved method for the binarization of data in an MPEG data stream. The invention makes use of unary binarization to create codewords up until an index threshold. Once the threshold has been met, succeeding code symbols have appended to them an exp-Golomb suffix. This hybrid binarization scheme reduces the number of binary codewords to be processed by a Binary Arithmetic Coder (BAC), thus reducing the computation required by the BAC.

Claims (34)

1. A method for generating an index value from a codeword for digital video decoding, comprising the steps of:

(A) setting said index value to a threshold in response to a first portion of said codeword having a first pattern;

(B) adding an offset to said index value based on a second pattern in a second portion of said codeword following said first portion in response to said first portion having said first pattern; and

(C) adding a value to said index value based on a third pattern in a third portion of said codeword following said second portion in response to said first portion having said first pattern.

2. The method according to claim 1 , further comprising the step of:

generating said index value based on a fourth pattern in said first portion in response to said fourth pattern being other than said first pattern.

3. The method according to claim 2 , wherein said first pattern is a predetermined pattern unique from all possible representations of said fourth pattern.

4. The method according to claim 2 , wherein said fourth pattern comprises (i) between zero and a plurality of first bits having a first state and (ii) a second bit having a second state opposite said first state.

5. The method according to claim 4 , wherein said second bit follows said first bits.

6. The method according to claim 1 , wherein said first pattern comprises a plurality of bits each having a first state.

7. The method according to claim 1 , wherein said second pattern comprises between zero and a plurality of first bits having a first state and (ii) a second bit having a second state opposite said first state.

8. The method according to claim 1 , wherein said third pattern comprises a binary number.

9. The method according to claim 1 , wherein said codeword in compatible with at least one of an International Organization for Standardization/International Electrotechnical Commission 14496-10 standard and an International Telecommunication Union-Telecommunications Standardization Sector Recommendation H.264.

10. The method according to claim 1 , further comprising the step of:

generating said index value based on a fourth pattern in said first portion in response to said fourth pattern being other than said first pattern, wherein (i) said first pattern comprises a plurality of bits each having a first state, (ii) said first pattern is unique from all possible representations of said fourth pattern, (iii) each of said representations of said fourth pattern ends in a bit having a second state opposite said first state and (iv) said second pattern has a same number of bits as said third pattern.

11. A system comprising:

a decoder configured to generate a codeword; and

a circuit configured to (i) set an index value to a threshold in response to a first portion of said codeword having a first pattern, (ii) add an offset to said index value based on a second pattern in a second portion of said codeword following said first portion in response to said first portion having said first pattern and (iii) add a value to said index value based on a third pattern in a third portion of said codeword following said second portion in response to said first portion having said first pattern.

12. A method for generating a codeword from an index value for digital video encoding, comprising the steps of:

(A) generating a first pattern in a first portion of said codeword in response to said index value being at least as great as a threshold;

(B) generating a second pattern in a second portion of said codeword following said first portion representing an offset of said index value above said threshold; and

(C) generating a third pattern in a third portion of said codeword following said second portion representing a value of said index value above said offset.

13. The method according to claim 12 , further comprising the step of:

generating a fourth pattern in said first portion based on said index value in response to said index value being below said threshold.

14. The method according to claim 13 , wherein said first pattern is a predetermined pattern unique from all possible representations of said fourth pattern.

15. The method according to claim 13 , wherein said fourth pattern comprises (i) between zero and a plurality of first bits having a first state and (ii) a second bit having a second state opposite said first state.

16. The method according to claim 12 , wherein (i) said offset has a first representation and (ii) said value has a second representation different than said first representation.

17. The method according to claim 12 , wherein said second pattern has a same number of bits as said third pattern.

18. The method according to claim 12 , wherein said second portion is void in response to said index value being below said threshold.

19. The method according to claim 12 , wherein said third portion is void in response to said index value being below said threshold.

20. The method according to claim 12 , wherein said codeword in compatible with at least one of an International Organization for Standardization/International Electrotechnical Commission 14496-10 standard and an International Telecommunication Union-Telecommunications Standardization Sector Recommendation H.264.

21. A system comprising:

a circuit configured to (i) generate a first pattern in a first portion of a codeword in response to an index value being at least as great as a threshold, (ii) generate a second pattern in a second portion of said codeword following said first portion representing an offset of said index value above said threshold and (iii) generating a third pattern in a third portion of said codeword following said second portion representing a value of said index value above said offset; and

an encoder configured to encode said codeword.

Assignments (9)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 10, 2020
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
To: BROADCOM CORPORATION
Reel/Frame 052065/0838 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0097. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048555/0510 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0097 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 17, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 034974/0873 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
CHANGE OF NAME Recorded Mar 9, 2012
From: LSI LOGIC CORPORATION
To: LSI CORPORATION
Reel/Frame 027836/0054 →