Remote sensed pre-amplifier for cross-point arrays
View Patent ↗In a particular embodiment, there are a plurality of parallel electrically conductive rows and a plurality of parallel electrically conductive columns crossing the rows, thereby forming a cross-point array with a plurality of intersections. Resistive devices, such as magnetic memory cells, also known as spin valve memory cells, are provided in electrical contact with and located at each intersection. A feedback controlled sense pre-amplifier is also provided to maintain an equi-potential for a given memory cell. A reference voltage is provided to the sense pre-amplifier. As voltage potential, VA′, is provided to the first end of a selected column, contacting a selected memory cell, a feedback voltage VA is provided to the sense pre-amplifier by an independent sense path. The independent sense path connects to the second end of the selected column. The sense pre-amplifier adjusts the applied potential VA to minimize the difference between the feedback and reference voltage.
1. A data storage device comprising:
a cross-point array of resistive devices; and
a feedback controlled sense pre-amplifier receiving a reference voltage and feedback from the cross-point array when a potential is applied to a selected resistive device within the array, the sense pre-amplifier adjusting the applied potential to minimize the difference between the feedback and reference voltage;
wherein the feedback is received from an independent sense path.
2. The data storage device of claim 1 , wherein the feedback controlled sense pre-amplifier is an equi-potential sense pre-amplifier.
3. The data storage device of claim 1 , wherein the cross-point array includes:
a plurality of parallel electrically conductive rows; and
a plurality of parallel electrically conductive columns crossing the rows, each thereby forming a cross point array with a plurality of intersections;
wherein each resistive device is in electrical contact with and located at an intersection between a row and column.
4. The data storage device of claim 3 , wherein each column has a first end and a second end, and a select element coupled to each end.
5. The data storage device of claim 4 , wherein the feedback is obtained from the select element at the second end of a selected column, and the potential is applied to the select element at the first end of the selected column.
6. The data storage device of claim 3 , wherein the resistive devices are magnetic memory cells, each memory cell including:
at least one ferromagnetic data layer characterized by an alterable orientation of magnetization;
an intermediate layer in contact with the data layer; and
at least one ferromagnetic reference layer in contact with the intermediate layer, opposite from the data layer.
7. The data storage device of claim 6 , wherein the reference layer is a soft-reference layer.
8. A resistive cross-point array comprising:
a plurality of parallel electrically conductive rows, each having a first and second end;
a plurality of parallel electrically conductive columns crossing the rows, each having a first and second end, thereby forming a cross point array with a plurality of intersections;
a plurality of resistive devices, each device in electrical contact with and located at an intersection between a row and column;
a feedback controlled sense pre-amplifier receiving a reference voltage and a feedback voltage from the second end of a selected column when a potential is applied to a selected resistive device connected to the first end of the selected column, the sense pre-amplifier adjusting the applied potential to minimize the difference between the feedback and reference voltage.
9. The resistive cross-point array of claim 8 , wherein the potential is applied to the first end of the selected column.
10. The resistive cross-point array of claim 8 , wherein the feedback controlled sense pre-amplifier is an equi-potential sense pre-amplifier.
11. The resistive cross-point array of claim 8 , wherein the feedback is received from an independent sense path.
12. The resistive cross-point array of claim 8 , wherein the resistive devices are magnetic memory cells, each memory cell including:
at least one ferromagnetic data layer characterized by an alterable orientation of magnetization;
an intermediate layer in contact with the data layer; and
at least one ferromagnetic reference layer in contact with the intermediate layer, opposite from the data layer.
13. The resistive cross-point array of claim 12 , wherein the reference layer is a soft-reference layer.
14. The resistive cross-point array of claim 8 , further including a circuit for sensing resistance states of a selected resistive device during read operations on the selected resistive device, the circuit;
applying a first voltage to the first end of a selected row conductor;
applying a second voltage to at least a subset of unselected row and unselected column conductors;
applying a third voltage to the first end of a selected column conductor, the third voltage being substantially equi-potential to the second voltage;
sensing a feedback voltage from the second end of the selected column conductor; and
adjusting the third voltage by the feedback controlled sense pre-amplifier to minimize the difference between the feedback and reference voltage.
15. The resistive cross-point array of claim 14 , wherein the third voltage is adjusted as the resistance state of the resistive device is changed.
16. The resistive cross-point array of claim 14 , wherein the reference voltage applied to the feedback controlled sense pre-amplifier is substantially equal to the second voltage.
17. A magnetic memory device with remote sensed pre-amplifier comprising:
a plurality of parallel electrically conductive rows, each having a first and second end;
a plurality of parallel electrically conductive columns crossing the rows, each having a first and second end, thereby forming a cross point array with a plurality of intersections;
a plurality of magnetic memory cells, each cell in electrical contact with and located at an intersection between a row and column;
a feedback controlled sense pre-amplifier receiving a reference voltage and feedback from the second end of a selected column when a potential is applied to a selected memory cell connected to the first end of the selected column, the sense pre-amplifier adjusting the applied potential to minimize the difference between the feedback and reference voltage.
18. The magnetic memory device of claim 17 , wherein the each memory cells includes:
at least one ferromagnetic data layer characterized by an alterable orientation of magnetization;
an intermediate layer in contact with the data layer; and
at least one ferromagnetic reference layer in contact with the intermediate layer, opposite from the data layer.
19. The magnetic memory device of claim 18 , wherein the reference layer is a soft-reference layer.
20. The magnetic memory device of claim 17 , wherein the feedback is received from an independent sense path.
21. The magnetic memory device of claim 17 , wherein including a circuit for sensing resistance states of a selected memory cell during read operations on the selected memory cell, the circuit;
applying a first voltage to the first end of a selected row conductor;
applying a second voltage to at least a subset of unselected row and unselected column conductors;
applying a third voltage to the first end of a selected column conductor, the third voltage being substantially equi-potential to the second voltage;
sensing a feedback voltage from the second end of the selected column conductor; and
adjusting the third voltage by the feedback controlled sense pre-amplifier to minimize the difference between the feedback and reference voltage.
22. The magnetic memory device of claim 21 , wherein the third voltage is adjusted as the resistance state of the selected memory cell is changed.
23. The magnetic memory device of claim 21 , wherein the reference voltage applied to the feedback controlled sense pre-amplifier is substantially equal to the second voltage.
24. A computer system comprising:
a main board;
at least one central processing unit (CPU) coupled to the main board; and
at least one memory store joined to the CPU by the main board, the memory store including;
a plurality of parallel electrically conductive rows, each having a first and second end;
a plurality of parallel electrically conductive columns crossing the rows, each having a first and second end, thereby forming a cross point array with a plurality of intersections;
a plurality of magnetic memory cells, each cell in electrical contact with and located at an intersection between a row and column;
a feedback controlled sense pre-amplifier receiving a reference voltage and feedback from the second end of a selected column when a potential is applied to a selected memory cell connected to the first end of the selected column, the sense pre-amplifier adjusting the applied potential to minimize the difference between the feedback and reference voltage.
25. The computer system of claim 24 , wherein the feedback is received from an independent sense path.
26. The computer system of claim 24 , wherein the memory store further includes a circuit for sensing resistance states of a selected memory cell during read operations on the memory cell, the circuit;
applying a first voltage to the first end of a selected row conductor applying a second voltage to at least a subset of unselected row and unselected column conductors;
applying a third voltage to the first end of a selected column conductor, the third voltage being substantially equi-potential to the second voltage;
sensing a feedback voltage from the second end of the selected column conductor; and
adjusting the third voltage by the feedback controlled sense pre-amplifier to minimize the difference between the feedback and reference voltage.