Method for making MOSFET anti-fuse structure
View Patent ↗An anti-fuse device includes a substrate and laterally spaced source and drain regions formed in the substrate. A channel is formed between the source and drain regions. A gate and gate oxide are formed on the channel and lightly doped source and drain extension regions are formed in the channel. The lightly doped source and drain regions extend across the channel from the source and the drain regions, respectively, occupying a substantial portion of the channel. Programming of the anti-fuse is performed by application of power to the gate and at least one of the source region and the drain region to break-down the gate oxide, which minimizes resistance between the gate and the channel.
1. A method of programming an anti-fuse device, comprising:
forming a channel between a source region laterally spaced from a drain region in a substrate;
forming a gate oxide on the channel;
forming a gate on the gate oxide;
forming lightly doped source and drain extension regions in the channel that cumulatively occupy substantially all of the channel before programming of the anti-fuse device; and
programming the anti-fuse device through application of power to the gate and one of the source region and the drain region, such that the gate oxide is broken down and resistance between the gate and the channel is minimized.
2. The method of claim 1 , further comprising providing a lightly doped P-type substrate as the substrate.
3. The method of claim 1 , further comprising doping the source and drain regions with N-type material.
4. The method of claim 1 , further comprising doping the lightly doped source and drain extension regions with N-type material.
5. The method of claim 1 , further comprising doping the source and drain regions with P-type material.
6. The method of claim 1 , further comprising doping the lightly doped source and drain extension regions with P-type material.
7. The method of claim 1 , further comprising forming a deep N-well region in the substrate below the source region, the drain region, and the channel.
8. The method of claim 1 , further comprising forming a deep P-well region in the substrate below the source region, the drain region, and the channel.
9. The method of claim 1 , further comprising:
doping the substrate with P-type material; and
forming the source and the drain regions in an N-well region formed in the substrate.
10. The method of claim 1 , further comprising forming an overlap region within the channel, wherein the overlap region includes the lightly doped source and drain extension regions.