IP Library Granted Patent US 6,919,614
Granted Patent B2
US 6,919,614 · App. 10/774,896 · Granted Jul 19, 2005

Circuit with an integrated voltage regulator and its manufacturing process

Assignee: STMicroelectronics S.A.
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Quick Facts
Patent No.
US 6,919,614
App. No.
10/774,896
Granted
Jul 19, 2005
Kind
B2
Abstract

An integrated circuit with a D.C./D.C. voltage regulator and its manufacturing process, including at least one power stage provided with at least two transistors and with at least one capacitor connecting a control electrode of the transistor to a reference voltage, a same control stage of the regulator providing a control signal of said transistors, the power stage being formed under a rail that provides supply signals of the integrated circuit, the rail providing at least two limiting supply voltages coming from the outside of the integrated circuit and at least one voltage regulated by the voltage regulator.

Claims (18)

1. An integrated circuit with a D.C./D.C. voltage regulator comprising at least one power stage provided with at least two transistors and with at least one capacitor connecting a control electrode of the transistor to a reference voltage, a same control stage of the regulator providing a control signal of said transistors, wherein the power stage is formed under a rail that provides supply signals of the integrated circuit, said rail providing at least two limiting supply voltages coming from the outside of the integrated circuit and at least one voltage regulated by said voltage regulator.

2. The circuit of claim 1 , wherein said rail further provides said control signal.

3. The circuit of claim 1 , wherein said transistors are formed in an active area underlying two close conductors that provides one of the limiting voltages and of said regulated voltage.

4. The circuit of claim 1 , wherein said capacitor is formed straight above a conductor providing a reference voltage corresponding to one of said limiting voltages.

5. The circuit of claim 1 , wherein the control electrodes of the transistors are formed of parallel conductive strips arranged perpendicularly to the conductors of said rail.

6. The circuit of claim 1 , wherein said voltages are provided in a first metallization level of the integrated circuit.

7. The circuit of claim 1 , wherein said control stage is formed in a core of the integrated circuit, around which is arranged said rail in a crown of circuit inputs/outputs.

8. A method for forming at least one power stage of a voltage regulator of an integrated circuit, the at least one power stage being formed of at least two MOS transistors and of at least one capacitor connecting a control electrode of said transistors to a reference voltage, comprising forming said transistors under a rail that provides supply signals of the integrated circuit, in a crown of inputs/outputs thereof, said rail providing at least said reference voltage, a regulated voltage provided by the power stages, and a supply voltage thereof.

9. The method of claim 8 , wherein said capacitor is formed under said rail.

10. An integrated circuit comprising at least one power stage provided with at least two transistors and with at least one capacitor for connecting a control electrode of the transistor to a reference voltage, a same control stage of a regulator providing a control signal of said transistors, wherein the power stage is formed under a rail that provides supply signals of the intregrated circuit, said rail is providing at least two limiting supply voltages coming from the outside of the integrated circuit and at least one regulated voltage.

11. The circuit of claim 10 , wherein said rail further provides said control signal.

12. The circuit of claim 10 , wherein said transistors are formed in an active area underlying two close conductors that provides one of the limiting voltages and of said regulated voltage.

13. The circuit of claim 10 , wherein said capacitor is formed straight above a conductor providing a reference voltage corresponding to one of said limiting voltages.

14. The circuit of claim 10 , wherein the control electrodes of the transistors are formed of parallel conductive strips arranged perpendicularly to the conductors of said rail.

15. The circuit of claim 10 , wherein said voltages are provided in a first metallization level of the integrated circuit.

16. The circuit of claim 10 , wherein said control stage is formed in a core of the integrated circuit, around which is arranged said rail in a crown of circuit inputs/outputs.

17. A method for forming at least one power stage of a voltage regulator of an integrated circuit, the at least one power stage being formed of at least two MOS transistors and of at least one capacitor for connecting a control electrode of said transistors to a reference voltage, comprising forming said transistors under a rail that provides supply signals of the integrated circuit, in a crown of inputs/outputs thereof.

18. The method of claim 17 , wherein said capacitor is formed under said rail.

Assignments (2)
CHANGE OF NAME Recorded Jan 21, 2024
From: STMICROELECTRONICS SA
To: STMICROELECTRONICS FRANCE
Reel/Frame 066357/0381 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 9, 2004
From: BLISSON, FABRICE; DEBEURME, GILLES
To: STMICROELECTRONICS, S.A.
Reel/Frame 014979/0386 →
Priority Claims (1)
FR 03 01624 · Feb 11, 2003 · national
Continuity (1)
Related Publication 20040159894A1 · Aug 19, 2004