System and method generating a delayed clock output
View Patent ↗The system and method generates two clock signals, one with a 2 ns delay with respect to the other, from a single PLL to enable a RGMII.
1. A method, comprising:
generating a first clock signal;
generating a plurality of clock signals, each having different phases;
generating a second clock signal based on the plurality of clock signals, the second clock signal having a different phase from the first clock signal; and
outputting the first and second clock signals,
wherein the generating a second clock uses phase interpolation.
2. A method, comprising:
generating a first clock signal;
generating a plurality of clock signals, each having different phases;
generating a second clock signal based on the plurality of clock signals, the second clock signal having a different phase from the first clock signal; and
outputting the first and second clock signals,
wherein the outputting outputs the first and second clock signals to a RGMII.
3. The method of claim 2 , wherein the second clock signal has about a 2 ns delay with respect to the first clock signal.
4. A method, comprising:
generating a first clock signal;
generating a plurality of clock signals, each having different phases;
generating a second clock signal based on the plurality of clock signals, the second clock signal having a different phase from the first clock signal; and
outputting the first and second clock signals,
wherein the first and second clock signals include 125 MHz clock signals.
5. A system, comprising:
means for generating a first clock signal;
means for generating a plurality of clock signals, each having different phases;
means for generating a second clock signal based on the plurality of clock signals, the second clock signal having a different phase from the first clock signal; and
means for outputting the first and second clock signals,
wherein the generating a second clock uses phase interpolation.
6. A system, comprising:
a PLL capable of generating a first clock signal;
a plurality of clock generators, communicatively coupled to the PLL, capable of generating a plurality of clock signals; and
an analog phase interpolator, communicatively coupled to the plurality of clock generators, capable of generating a second clock signal based on the plurality of clock signals, the second clock signal having a different phase from the first clock signal.
7. The system of claim 6 , wherein the generating a second clock uses phase interpolation.
8. The system of claim 6 , further comprising an RGMII capable of receiving the first and second clock signals.
9. The system of claim 8 , wherein the second clock signal has about a 2 ns delay with respect to the first clock signal.
10. The system of claim 6 , wherein the first and second clock signals include 125 MHz clock signals.
11. The system of claim 6 , wherein the plurality of clock signals is based on the first clock signal.
12. The system of claim 6 , wherein the plurality of signals includes eight signals.
13. A switch comprising a system according to claim 6 .