IP Library Granted Patent US 7,172,980
Granted Patent B2
US 7,172,980 · App. 10/781,565 · Granted Feb 6, 2007

Process for fabricating an integrated electronic circuit that incorporates air gaps

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Quick Facts
Patent No.
US 7,172,980
App. No.
10/781,565
Granted
Feb 6, 2007
Kind
B2
Abstract

A process for fabricating an integrated electronic circuit comprises the formation of at least one air gap between interconnect elements above only a defined portion of a surface of a substrate, within an interconnect layer. The interconnect layer comprises a sacrificial material and extends beneath an intermediate layer of permeable material. The air gap is formed by removal, through the intermediate layer, of at least part of the sacrificial material by bringing the permeable material into contact with an agent for removing the sacrificial material, to which agent the permeable material is resistant.

Claims (32)

1. A process for fabricating an integrated electronic circuit, said integrated circuit having

a substrate,

an intermediate layer of permeable material,

an interconnect layer comprising initially a part of a sacrificial material and extending beneath the intermediate layer, and

interconnect elements formed within a subpart of said part of sacrificial material of the interconnect layer,

the process comprising: forming at least one air gap within the interconnect layer by removing, through the intermediate layer, at least said subpart of sacrificial material of the interconnect layer by bringing the permeable material into contact with an agent for removing the sacrificial material, to which agent the permeable material is resistant, said intermediate layer remaining rigidly linked to the substrate outside said defined portion;

whereby the at least one air gap is formed above only a defined portion of a surface of a substrate, and said defined portion being smaller than the surface of the substrate.

2. The process according to claim 1 , comprising the following steps:

a) a first part of the interconnect layer is formed with a permanent material outside said portion of the surface of the substrate;

b) a second part of the interconnect layer is formed with the sacrificial material inside said portion of the surface of the substrate;

c) the interconnect elements are formed within the second part of the interconnect layer;

d) the intermediate layer of permeable material is deposited on the interconnect layer at least above said portion (P) of the surface of the substrate; and

e) all of the sacrificial material of the interconnect layer is removed through the intermediate layer.

3. The process according to claim 2 , whereby the permanent material ( 10 ) is identical to the permeable material.

4. The process according to claim 2 , whereby step b) of forming the second part of the interconnect layer is carried out before step a) of forming the first part of the interconnect layer.

5. The process according to claim 4 , whereby the permanent material ( 10 ) is identical to the permeable material.

6. The process according to claim 2 , whereby step a) of forming the first part of the interconnect layer, step b) of forming the second part of the interconnect layer, step c) of forming the interconnect elements and step d) of depositing the intermediate layer are repeated several times before step e) of removing the sacrificial material, so as to form, above the surface of the substrate, a stack comprising several interconnect layers separated by intermediate layers of permeable material and comprising respective layers of sacrificial material above respective portions of the surface of the substrate and whereby, during step e) of removing the sacrificial material, the sacrificial material of the interconnect layers is removed by bringing the permeable material of the intermediate layers into contact with the agent for removing the sacrificial material so as to form respective air gaps in each of the interconnect layers.

7. The process according to claim 1 , comprising the following steps:

a) the interconnect layer is formed with the sacrificial material on the surface of the substrate inside said portion;

b) the interconnect elements are formed within the interconnect layer;

c) the intermediate layer of permeable material is deposited on the interconnect layer in said portion of the surface of the substrate and on the surface of the substrate around the interconnect layer, outside said portion of the surface of the substrate; and

d) all of the sacrificial material of the interconnect layer is removed through the intermediate layer.

8. The process according to claim 7 , whereby step a) of forming the interconnect layer, step b) of forming the interconnect elements and step c) of depositing the intermediate layer are repeated several times before step d) of removing the sacrificial material, so as to form, above the surface of the substrate, a stack comprising several interconnect layers that are separated by intermediate layers of permeable material and are surrounded, parallel to the surface of the substrate, by permeable material outside respective portions of the surface of the substrate and whereby, during step d) of removing the sacrificial material, the sacrificial material of the interconnect layers is removed by bringing the permeable material of the intermediate layers into contact with the agent for removing the sacrificial material so as to form respective air gaps in each of the interconnect layers.

9. The process according to claim 1 , comprising the following steps:

a) the interconnect layer is formed with the sacrificial material on the surface of the substrate inside and outside said portion;

b) the interconnect elements are formed within the interconnect layer above said portion of the surface of the substrate;

c) an intermediate layer of permeable material is deposited on the interconnect layer inside and outside said portion of the surface of the substrate;

d) a mask impermeable to the agent for removing the sacrificial material is formed above the intermediate layer, the mask having an aperture corresponding to said portion of the surface of the substrate; and

e) part of the sacrificial material of the interconnect layer is selectively removed through the intermediate layer, the selectively removed part of the sacrificial material being bounded by the mask in a direction parallel to the surface of the substrate.

10. The process according to claim 9 , whereby the mask is formed on the intermediate layer of permeable material.

11. The process according to claim 9 , whereby step a) of forming the interconnect layer, step b) of forming the interconnect elements and step c) of depositing the intermediate layer are repeated several times before step d) of forming the mask, so as to form, above the surface of the substrate, a stack comprising several interconnect layers that are separated by intermediate layers of permeable material and whereby, during step e) of removing the sacrificial material, part of the sacrificial material of the interconnect layers is selectively removed by bringing, via the aperture of the mask, the permeable material of the intermediate layers into contact with the agent for removing the sacrificial material so as to form respective air gaps in each of the interconnect layers.

12. The process according to claim 1 , whereby, during formation of the interconnect elements, a layer of a baffler material covering at least part of the faces of the interconnect elements is formed.

Assignments (6)
CHANGE OF NAME Recorded Jan 19, 2024
From: STMICROELECTRONICS SA
To: STMICROELECTRONICS FRANCE
Reel/Frame 066355/0645 →
RELEASE OF SECURITY INTEREST Recorded Sep 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050315/0785 →
SECURITY AGREEMENT Recorded Jun 17, 2009
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 022835/0306 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 28, 2009
From: KONINKLIJKE PHILIPS ELECTRONICS N.V.
To: NXP B.V.
Reel/Frame 022597/0832 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 16, 2004
From: TORRES, JOAQUIN; ARNAL, VINCENT
To: STMICROELECTRONICS SA.
Reel/Frame 015566/0125 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 16, 2004
From: GOSSET, LAURENT
To: KONINKLIJKE PHILIPS ELECTRONICS N.V.
Reel/Frame 015566/0161 →