Patent Assignment
Reel/Frame 022597/0832
Assignment of Assignor's Interest
Recorded: 2009-04-28
Received: 2009-04-28
Pages: 7
Assignor
KONINKLIJKE PHILIPS ELECTRONICS N.V.
Executed: 2009-04-09
Assignee
NXP B.V.
HIGH TECH CAMPUS 60, 5656 AG EINDHOVEN, NLX, NETHERLANDS
Covered Properties
(31)
Anti-Fuse Cell and Its Manufacturing Process
Application:
11/722,974 →
Integration of Self-Aligned Trenches in-Between Metal Lines
Application:
12/161,456 →
Microelectromechanical device packaging with an anchored cap and its manufacture
Application:
11/991,041 →
Method for Forming Metal Interconnects in a Dielectric Material
Application:
12/280,978 →
Cusin/Sin Diffusion Barrier for Copper in Integrated-Circuit Devices
Application:
12/439,910 →
Control of Carbon Nanostructure Growth in an Interconnect Structure
Application:
12/439,919 →
Co-Integration of Multi-Gate Fet with Other Fet Devices in Cmos Technology
Application:
12/296,402 →
Semiconductor Device Including a Coupled Dielectric Layer and Metal Layer, Method of Fabrication Thereof, and Passivating Coupling Material Comprising Multiple Organic Components for Use in a Semiconductor Device
Application:
12/280,477 →
On-Chip Interconnect-Stack Cooling Using Sacrificial Interconnect Segments
Application:
12/158,989 →
Capping Layer Formation Onto a Dual Damescene Interconnect
Application:
12/065,190 →
Semiconductor Device Including a Coupled Dielectric Layer and Metal Layer, Method of Fabrication Thereof, and Material for Coupling a Dielectric Layer and a Metal Layer in a Semiconductor Device
Application:
12/065,179 →
Dual Gate Field Effect Transistor
Application:
11/960,382 →
Integrated Circuit Comprising a Capacitor with Metal Electrodes and Process for Fabricating Such a Capacitor
Application:
11/570,731 →
Apparatus for Cleaning of Circuit Substrates
Application:
11/912,126 →
Method and Apparatus for Forming a Semiconductor Substrate with a Layer Structure of Activated Dopants
Application:
11/744,574 →
Process for Fabricating an Electronic Integrated Circuit and Electronic Integrated Circuit Thus Obtained
Application:
10/589,275 →
Integration Control and Reliability Enhancement of Interconnect Air Cavities
Application:
11/456,657 →
Controlling Lateral Distribution of Air Gaps in Interconnects
Application:
11/482,520 →
Method for Fabrication of in-Laid Metal Interconnects
Application:
10/526,422 →
Method of Fabricating an Integrated Circuit Including Hollow Isolating Trenches and Corresponding Integrated Circuit
Application:
11/110,359 →
Method for the formation of silicides
Application:
10/871,542 →
Process for Fabricating an Integrated Electronic Circuit That Incorporates Air Gaps
Application:
10/781,565 →
Deep Insulating Trench
Application:
10/479,639 →
Electrical Connection Device Between Two Tracks of an Integrated Circuit
Application:
10/714,442 →
Process for Fabricating an Electrical Circuit Comprising a Polishing Step
Application:
10/651,492 →
Railcar Mover Having Negative Cambered Rail Wheels
Application:
10/298,028 →
Process for Forming Shallow Isolating Regions in an Integrated Circuit and an Integrated Circuit Thus Formed
Application:
09/933,784 →
Process for Forming a Low Resistivity Titanium Silicide Layer on a Silicon Semiconductor Substrate and the Resulting Device
Application:
09/858,400 →
Mos Transistor in an Integrated Circuit and Active Area Forming Method
Application:
09/823,274 →
Method of Forming an Insulating Zone
Application:
09/816,485 →
Process for Fabricating an Integrated Circuit
Application:
09/790,259 →