Control of carbon nanostructure growth in an interconnect structure
View Patent ↗An interconnect structure on a substrate is provided. The interconnect structure comprises electrically conductive interconnect elements on at least two interconnect levels on or above a substrate level. In the interconnect structure of the invention, at least one electrically conductive via connects a first interconnect element on one interconnect level or on the substrate level to a second interconnect element on a different interconnect level. The via extends in a via opening of a first dielectric layer and comprises an electrically conductive via material that contains electrically conductive cylindrical carbon nanostructures. At least one cover-layer segment reaches into a lateral extension of the via opening and defines a via aperture that is small enough to prevent a penetration of the carbon nanostructures through the via aperture. This structure enhances control of carbon nanostructure growth in a height direction during fabrication of the interconnect structure.
1. An interconnect structure on a substrate, with electrically conductive interconnect elements on at least two interconnect levels on or above a substrate level, wherein
at least one electrically conductive via connects a first interconnect element on one interconnect level or on the substrate level to a second interconnect element on a different interconnect level, the via extending in a via opening of a first dielectric layer and comprising an electrically conductive via material that contains electrically conductive cylindrical carbon nanostructures, and wherein
at least one cover-layer segment reaches into a lateral extension of the via opening and defines a via aperture over the via opening, wherein the via aperture is small enough to prevent a penetration of the carbon nanostructures through the via aperture.
2. The interconnect structure of claim 1 , wherein the via material comprises carbon nanotubes or carbon nanowires, and wherein the via aperture is smaller than or equal to twice an outer cylinder diameter of a single carbon nanotube or carbon nanowire.
3. The interconnect structure of claim 1 , wherein the via material comprises carbon nanotubes or carbon nanowires, and wherein the via aperture is smaller than or equal to an outer cylinder diameter of a single carbon nanotube or carbon nanowire.
4. The interconnect structure of claim 1 , wherein the at least one cover-layer segment is arranged at a first via end of the via, which is more distant from the substrate than a second via end of the via.
5. The interconnect structure of claim 1 , wherein the via material in the via opening is seated on a catalytic layer, which is suitable for supporting growth of the carbon nanostructures.
6. The interconnect structure of claim 1 , wherein the cover-layer segment is made of a dielectric material.
7. The interconnect structure of claim 1 , wherein the cover-layer segment is arranged on a dielectric liner.
8. The interconnect structure of claim 1 , wherein the cover-layer segment covers a top section of a sidewall of the via opening and laterally abuts to a dielectric liner that is arranged between the second interconnect element and the first dielectric layer outside the via opening.
9. The interconnect structure of claim 1 , wherein the cover-layer segment forms a section of a cover layer that covers a bottom face of a first interconnect opening in the first dielectric layer, which interconnect opening is filled by the second interconnect element.
10. The interconnect structure of claim 1 , wherein the via material comprises carbon nanotubes or carbon nano wires, which have an orientation of their longitudinal axis in a height direction pointing from the first to the second interconnect element.
11. A method for fabricating an interconnect structure that has a via connecting a first electrically conductive interconnect element on one interconnect level or on the substrate level and a second interconnect element on a different interconnect level, comprising the steps of:
providing a substrate with the first interconnect element on one interconnect level or on the substrate level;
depositing a first dielectric layer on the first interconnect element;
fabricating, in the dielectric layer, a via opening that reaches to the first interconnect element;
fabricating a cover-layer segment on the first dielectric layer that reaches into a lateral extension of the via opening and defines a via aperture over the via opening;
fabricating an electrically conductive via material that contains electrically conductive cylindrical carbon nanostructures in the via opening; and
fabricating the second interconnect element that contacts the via;
wherein the via aperture is made small enough to prevent a penetration of the carbon nanostructures through the via aperture.
12. The method of claim 11 , comprising, before the step of fabricating the via material in the via opening, a step of fabricating a catalytic layer, which is suitable for supporting growth of the carbon nanostructures, on a bottom face of the via opening.
13. The method of claim 11 , wherein the step of fabricating a cover-layer segment on the first dielectric layer comprises: non-conformally depositing a cover layer on a top face of the first dielectric layer.
14. The method of claim 12 , wherein the cover layer is selectively deposited, thus avoiding a deposition of the cover-layer material on a bottom face of the via opening.
15. The method of claim 12 , comprising a step of removing cover-layer material, which has been deposited during the step of non-conformally depositing the cover layer, from a bottom face of the via opening.
16. The method of claim 11 , comprising a step of removing the cover layer from the top face of the first dielectric layer outside the via opening.
17. The method of claim 11 , wherein the deposition of the via material in the via opening is sustained in height until the via material abuts to the cover-layer segment.
18. The method of claim 11 , which is performed as a part of a single- or dual-damascene process.
19. A method for fabricating an integrated-circuit device, comprising a step of fabricating an interconnect structure by means of the method of claim 11 .
20. The interconnect structure of claim 1 , wherein the via aperture is smaller than a lateral dimension of the via opening.