Controlling lateral distribution of air gaps in interconnects

1. A method of fabricating an integrated circuit, said method comprising the steps of:

producing an integrated circuit interconnect stack having at least one interconnect layer comprising a sacrificial material and a permeable material allowing diffusion of a removal agent;

defining a portion on a surface of the integrated circuit interconnect stack as being specific to air cavity introduction, the defined portion being smaller than the surface;

defining at least one trench area surrounding the defined portion of the surface of the integrated circuit interconnect stack and forming at least one trench within the integrated circuit interconnect stack in the trench area;

depositing a first hard mask layer to coat the trench; and

forming at least one air cavity below the defined portion of the surface of the integrated circuit interconnect stack by using the removal agent for removing the sacrificial material to which the permeable material is resistant.

2. The method of fabricating an integrated circuit according to claim 1 , further comprising the step of thickening the trench by depositing a second hard mask layer.

3. The method of fabricating an integrated circuit according to claim 1 , further comprising the step of forming a plurality of conducting lines and vias within the integrated circuit interconnect stack before the step of forming the air cavity.

4. The method of fabricating an integrated circuit according to claim 1 , further comprising the step of controlling a lateral diffusion within the integrated circuit interconnect stack of the removal agent through the sacrificial material.

5. The method of fabricating an integrated circuit according to claim 1 , wherein in the step of forming at least one trench, the depth of the trench does not reach a bottom surface of the integrated circuit interconnect stack.

6. The method of fabricating an integrated circuit according to claim 1 , further comprising the step of forming an upper metal level subsequent to the step of forming at least one air cavity below the defined portion.

7. The method of fabricating an integrated circuit according to claim 6 , wherein the permeable layer is rigidly stabilized both by lower metal lines of the integrated circuit interconnect stack and by the upper metal level associated with the first hard mask layer subsequent to the step of forming the air cavity by using the removal agent.

8. The method of fabricating an integrated circuit according to claim 6 , wherein the step of forming the upper metal level comprises depositing an upper dielectric level using chemical vapor deposition or spin-on deposition.

9. The method of fabricating an integrated circuit according to claim 6 , further comprising the step of integrating a permeable layer allowing diffusion of the removal agent, as an isolating layer in the upper metal level.

10. A method of fabricating an integrated circuit, said method comprising the steps of:

producing an integrated circuit interconnect stack having at least one interconnect layer comprising a sacrificial material and a permeable material allowing diffusion of a removal agent;

defining a portion on a surface of the integrated circuit interconnect stack as being specific to air cavity introduction, the defined portion being smaller than the surface;

forming an additional permeable layer above the surface of the integrated circuit interconnect stack, and depositing a hard mask layer and a resist layer for a lithographic process;

etching the additional permeable layer and the hard mask layer using a mask suitable to expose at least one area where air cavities are not to be introduced;

performing a second lithographic step for defining the portion on the surface of the integrated circuit interconnect stack for air cavity introduction; and

forming at least one air cavity below the defined portion of the surface of the integrated circuit interconnect stack by using the removal agent for removing the sacrificial material to which the permeable material is resistant.

11. The method of fabricating an integrated circuit according to claim 10 , wherein the step of depositing the hard mask layer is performed using chemical vapor deposition.

12. The method of fabricating an integrated circuit according to claim 10 , further comprising the step of forming a plurality of conducting lines and vias within the integrated circuit interconnect stack before the step of forming the air cavity.

13. The method of fabricating an integrated circuit according to claim 10 , further comprising the step of controlling a lateral diffusion within the integrated circuit interconnect stack of the removal agent through the sacrificial material.

14. The method of fabricating an integrated circuit according to claim 10 , wherein in the step of forming at least one trench, the depth of the trench does not reach a bottom surface of the integrated circuit interconnect stack.

15. The method of fabricating an integrated circuit according to claim 10 , further comprising the step of forming an upper metal level subsequent to the step of forming at least one air cavity below the defined portion.

16. The method of fabricating an integrated circuit according to claim 15 , wherein the permeable layer is rigidly stabilized both by lower metal lines of the integrated circuit interconnect stack and by the upper metal level associated with the hard mask layer subsequent to the step of forming the air cavity by using the removal agent.

17. The method of fabricating an integrated circuit according to claim 15 , wherein the step of forming the upper metal level comprises depositing an upper dielectric level using chemical vapor deposition or spin-on deposition.

18. The method of fabricating an integrated circuit according to claim 15 , further comprising the step of integrating a permeable layer allowing diffusion of the removal agent, as an isolating layer in the upper metal level.