Generalized convolutional interleaver/deinterleaver
View Patent ↗A memory-efficient convolutional interleaver/deinterleaver with a memory array, a write commutator, and a read commutator wherein the commutators perform their respective write and read operations relative to a preselected memory cell after a predetermined delay. The delay is chosen using a modulo-based technique, such that an efficient implementation of a Ramsey Type-II interleaver is realized.
1. A convolutional interleaving system comprising:
a memory array having a plurality of array cells, M, with selected array cells storing symbols therein, the memory array having a memory block length, N, and an interleave depth, D;
a write commutator operably connected with the memory array for writing a symbol to a preselected memory cell at a first time; and
a read commutator operably connected with the memory array for reading the written symbol from the preselected memory cell at a second time, wherein a difference between the second time and the first time is a predetermined delay, the predetermined delay being related to a desired structure of the memory array,
wherein the memory array includes a plurality of interleaver array rows, the plurality of interleaver array rows including a selected row, R i , having a row length, S, determined by:
S
=
⌊
(
D
-
1
)
N
R
i
⌋
+
1
,
and
wherein i is the number of the row,
wherein M is determined by:
M
=
(
N
-
1
)
D
+
gcd
(
N
,
D
-
1
)
+
1
2
,
and
wherein gcd(N,D)=1.
2. The convolutional interleaving system of claim 1 , wherein one of the read commutator and the write commutator changes position using a predetermined modulo technique.
3. The convolutional interleaving system of claim 2 , wherein the predetermined modulo technique comprises incrementing the position of the one of the read commutator and the write commutator by K rows, wherein K>1.
4. The convolutional interleaving system of claim 2 , wherein the predetermined modulo technique comprises incrementing the position of the one of the read commutator and the write commutator by K rows, wherein K satisfies:
KDmodN≡1.
5. The convolutional interleaving system of claim 1 , wherein one of the read commutator and the write commutator changes position using a predetermined modulo technique, the predetermined modulo technique incrementing the position of the one of the read commutator and the write commutator by K rows, wherein K>1 and K satisfies:
KDmodN≡1.
6. The convolutional interleaving system of claim 5 , wherein the predetermined modulo technique comprises incrementing the position of the other of the read commutator and the write commutator by one cell.
7. The convolutional interleaving system of claim 1 , further comprising a row position pointer for selecting a memory cell within a selected one of the plural array rows.
8. The convolutional interleaving system of claim 1 , wherein the memory array further includes a plurality of deinterleaver array rows, the plurality of deinterleaver array rows including a selected row, R d , having a row length, U, determined by:
U
=
⌊
(
D
-
1
)
N
(
N
-
1
-
R
d
)
⌋
+
1
,
wherein d is the number of the row.
9. The convolutional interleaving system of claim 1 , wherein the predetermined delay is selectable among:
a. (D−1) (i mod N) symbols, wherein gcd(N,D)=1;
b. (N) (i mod D) symbols, wherein D|N;
c. (D−1) ((N-i−1) mod N) symbols, wherein gcd(N,D)=1; and
d. (N) ((D-i−1) mod D) symbols, wherein D|N.
10. The convolutional interleaving system of claim 1 , wherein the commutator position of one of the read commutator and the write commutator increments prior to a read operation.
11. The convolutional interleaving system of claim 1 , wherein the commutator position of one of the read commutator and the write commutator increments after a write operation.
12. The convolutional interleaving system of claim 1 , wherein one of the read commutator and the write commutator changes position using a predetermined finite difference equation technique.