IP Library Granted Patent US 7,093,226
Granted Patent B2
US 7,093,226 · App. 10/785,254 · Granted Aug 15, 2006

Method and apparatus of wafer print simulation using hybrid model with mask optical images

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Quick Facts
Patent No.
US 7,093,226
App. No.
10/785,254
Granted
Aug 15, 2006
Kind
B2
Abstract

To exam mask defect impact during the transfer of a mask pattern to a wafer layer, tools can use mask images obtained during mask inspection. Specifically, these tools can also use optical models of such mask images to simulate wafer images. However, when feature sizes become very small, optical models may not provide sufficiently accurate simulation results. Using a photoresist model would yield significantly more accurate simulation results than using an optical model. Unfortunately, resist modeling is very slow, thereby making it commercially impractical. A simulation tool can generate a simulated wafer image having the accuracy of a photoresist model with the speed of an optical model by using a threshold look-up table. In one embodiment, the threshold look-up table could include variables such as feature size, pitch size, feature type, and defect type.

Claims (38)

1. A method of automatically performing a wafer simulation, the method comprising:

receiving a mask image;

performing a wafer simulation of the mask image using an optical model;

characterizing a feature from the mask image;

obtaining threshold data from a look-up table (LUT) based on the characterizing, the LUT generated using a resist model and organized based on feature size, pitch size, and feature/defect identification; and

applying the threshold data to the wafer simulation to generate accurate wafer contours of the feature.

2. The method of claim 1 , wherein obtaining threshold data can indicate an exact match or a closest match in the LUT.

3. A method of automatically performing a wafer simulation, the method comprising:

receiving a mask image;

performing a wafer simulation of the mask image using a first model;

characterizing a feature from the mask image;

obtaining threshold data from a look-up table (LUT) based on the characterizing, the LUT generated using a second model more accurate than the first model and organized based on feature size, pitch size, and feature/defect identification; and

applying the threshold data to the wafer simulation to generate wafer contours of the feature.

4. The method of claim 3 , wherein obtaining threshold data can indicate an exact match or a closest match in the LUT.

5. A method of determining a wafer contour of a mask feature, the method comprising:

simulating the wafer contour by applying an optical model to the mask feature;

accessing resist information in a look-up table (LUT) to determine a threshold associated with the mask feature, the LUT organized based on feature size, pitch size, and feature/defect identification; and

improving an accuracy of the water contour using the threshold.

6. The method of claim 5 , wherein the LUT table includes optical information.

7. The method of claim 5 , wherein the LUT table includes etch information.

8. A computer-implemented program for generating a wafer contour, the program comprising:

code for receiving a mask image;

code for performing a wafer simulation of the mask image using an optical model;

code for characterizing a feature from the mask image;

code for obtaining threshold data from a look-up table (LUT) based on the characterizing, the LUT generated using a resist model and organized based on feature size, pitch size, and feature/defect identification; and

code for applying the threshold data to the wafer simulation to generate accurate wafer contours of the feature.

9. The program of claim 8 , wherein code for obtaining threshold data can provide at least one of an exact match in the LUT and a closest match in the LUT.

10. A method of creating a look-up table (LUT) for use in a wafer simulation, the method including:

receiving a test layout;

simulating the test layout using a resist model, which provides accurate wafer edge locations of features on the test layout;

simulating the test layout using an optical model, which provides aerial image information of the features on the test layout;

matching the accurate wafer edge locations of the features to the aerial image information of the features;

computing thresholds for a plurality of features based on the matching; and

storing the thresholds in the LUT organized based on feature size, pitch size, and feature/defect identification.

11. The method of claim 10 , wherein thresholds vary for different patterns, pitch sizes, feature sizes, and defect types.

12. The method of claim 10 , wherein the LUT can include the thresholds for more than one resist.

13. The method of claim 10 , wherein the aerial image information indicates light intensity as a function of position.

14. The method of claim 10 , wherein the test layout includes various patterns, pitch sizes, and feature sizes.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 21, 2009
From: NUMERICAL TECHNOLOGIES, INC.
To: SYNOPSYS MERGER HOLDINGS LLC
Reel/Frame 023683/0670 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2005
From: SYNOPSYS MERGER HOLDINGS LLC
To: SYNOPSYS, INC.
Reel/Frame 015653/0738 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 23, 2004
From: PANG, LINYONG
To: NUMERICAL TECHNOLOGIES, INC.
Reel/Frame 015019/0888 →