Electrical contact for optoelectronic semiconductor chip and method for its production
View Patent ↗An electrical contact for an optoelectronic device which includes a mirror layer ( 2 ) of a metal or a metal alloy, a protective layer ( 3 ), which serves for reducing the corrosion of the mirror layer ( 2 ), a barrier layer ( 4 ), a coupling layer ( 5 ), and a solder layer ( 8 ). A contact of this type is distinguished by high reflectivity, good ohmic contact with respect to the semiconductor, good adhesion on the semiconductor and good adhesion of the layers forming the contact with one another, good thermal stability, high stability with respect to environmental influences, and also solderability and patternability.
1. An electrical contact of an optoelectronic semiconductor chip ( 1 ), comprising:
a mirror layer ( 2 ) comprised of a metal or a metal alloy adapted to be formed over the semiconductor chip;
a protective layer ( 3 ) over said mirror layer ( 2 );
a layer sequence of a barrier layer ( 4 ) and a coupling layer ( 5 ) over said protective layer; and
a solder layer ( 8 ) over said layer sequence;
wherein said mirror layer, protective layer, layer sequence and solder layer are all electrically conductive so that current can flow through the electrical contact to and from the semiconductor chip.
2. The electrical contact as claimed in claim 1 , which includes a wetting layer ( 6 ) between the coupling layer ( 5 ) and the solder layer ( 8 ).
3. The electrical contact as claimed in claim 1 , which is applied to a surface of a semiconductor chip ( 1 ) having a nitride compound semiconductor material.
4. The electrical contact as claimed in claim 1 , in which the mirror layer ( 2 ) contains silver, aluminum or platinum.
5. The electrical contact as claimed in claim 1 , in which the mirror layer ( 2 ) is between 70 nm and 130 nm thick.
6. The electrical contact as claimed in claim 1 , in which a layer ( 13 ) of an electrically conductive material between 0.1 and 0.5 nm thin is included between the semiconductor chip ( 1 ) and the mirror layer ( 2 ) to improve the adhesion of the mirror layer ( 2 ).
7. The electrical contact as claimed in claim 6 , in which the surface of the semiconductor chip ( 1 ) has a nitride compound semiconductor material, the mirror layer ( 2 ) contains Al or Ag, and the thin layer ( 13 ) contains Pt, Pd or Ni.
8. The electrical contact as claimed in claim 1 , in which the protective layer ( 3 ) contains titanium or platinum.
9. The electrical contact as claimed in claim 1 , in which the protective layer ( 3 ) is between 5 nm and 15 nm thick.
10. The electrical contact as claimed in claim 1 , in which the barrier layer ( 4 ) completely covers the mirror layer ( 2 ) and the protective layer ( 3 ).
11. The electrical contact as claimed in claim 1 , in which the barrier layer ( 4 ) contains TiW(N).
12. The electrical contact as claimed in claim 1 , in which the barrier layer ( 4 ) is between 300 nm and 500 nm thick.
13. The electrical contact as claimed in claim 1 , in which the coupling layer ( 5 ) contains titanium.
14. The electrical contact as claimed in claim 1 , in which the coupling layer ( 5 ) is between 30 nm and 70 nm thick.
15. The electrical contact as claimed in claim 2 , in which the wetting layer ( 6 ) contains platinum.
16. The electrical contact as claimed in claim 2 , in which the wetting layer ( 6 ) is between 70 nm and 130 nm thick.
17. The electrical contact as claimed in claim 2 , in which a gold layer ( 7 ) is applied to the wetting layer ( 6 ).
18. The electrical contact as claimed in claim 1 , in which a gold layer ( 9 ) is applied to the solder layer ( 8 ).
19. The electrical contact as claimed in claim 18 , in which the gold layer ( 9 ) applied to the solder layer ( 8 ) is approximately 30 rim to 70 nm thick.
20. The electrical contact as claimed in claim 1 , which is adapted for connection of the semiconductor chip ( 1 ) to a carrier body, the material of the solder layer ( 8 ) being suitable for forming an alloy with the material of the carrier body.
21. The electrical contact as claimed in claim 20 , in which the solder layer ( 8 ) contains AuGe and the carrier body contains Ge.
22. The electrical contact as claimed in claim 20 , in which the solder layer ( 8 ) contains AuSi and the carrier body contains Si.
23. The electrical contact as claimed in claim 6 which is adapted for connection of the semiconductor chip ( 1 ) to a carrier body, the material of the solder layer ( 8 ) being suitable for forming an alloy with the material of the carrier body, and wherein said thin layer ( 13 ) comprises palladium or a nickel oxide.
24. The electrical contact as claimed in claim 1 , wherein said layer sequence comprises said barrier layer over said protective layer, and said coupling layer over said barrier layer.
25. The electrical contact as claimed in claim 20 , wherein said alloy is a eutectic alloy.