IP Library Granted Patent US 6,992,604
Granted Patent B2
US 6,992,604 · App. 10/791,534 · Granted Jan 31, 2006

Method and system for converting digital samples to an analog signal

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Quick Facts
Patent No.
US 6,992,604
App. No.
10/791,534
Granted
Jan 31, 2006
Kind
B2
Abstract

Provided is a system and method for converting digital data audio data audio data that has a predetermined input sample rate, into an analog data signal. A system includes a digital to analog converter (DAC) including a digital processing portion configured to receive as an input the digital audio data and timing information, the timing information being representative of a time base of the input sample rate. The digital processing portion is similarly configured to digitally process the digital audio data and the timing information to produce serialized output data. The DAC also includes an analog processing portion configured to convert serialized data to an analog format. The digital processing portion operates in accordance with at least one clock having a corresponding clock rate wherein the corresponding clock rate is unrelated to the input sample rate.

Claims (32)

1. A digital to analog converter (DAC) configured to convert input digital audio data to analog data, the digital audio data having a predetermined input sample rate, the DAC comprising:

a digital processing portion configured to (i) receive as an input the digital audio data and timing information, the timing information being representative of a time base of the input sample rate and (ii) digitally process the digital audio data and the timing information to produce serialized output data; and

an analog processing portion configured to convert the serialized output data to an analog format;

wherein the digital processing portion operates in accordance with at least one system clock having a corresponding system clock rate; and

wherein the at least one corresponding system clock rate is independent of the input sample rate.

2. The DAC of claim 1 , wherein the digital processing portion includes a rate manager and a rate converter.

3. The DAC of claim 2 , wherein the rate converter is asynchronous.

4. The DAC of claim 2 , wherein the rate manager receives the input sample rate data in accordance with the clock and produces an input sample rate value therefrom.

5. The DAC of claim 4 , wherein the value correlates the input sample rate with a desired output sample rate.

6. The DAC of claim 5 , wherein the value is a fractional value having ranges from −2 17 to 2 17 .

7. The DAC of claim 6 , wherein the fractional value is computed each period of the clock.

8. The DAC of claim 7 , wherein the rate converter performs at least one of decimating and interpolating the digital audio data based upon the fractional value.

9. The DAC of claim 4 , wherein the timing information includes system time clock (STC) pulses.

10. The DAC of claim 4 , wherein the digital processing portion is formed on a single integrated circuit chip.

11. The DAC of claim 4 , wherein the rate converter output audio samples at the desirable output sample rate.

12. The DAC of claim 11 , wherein the digital processing portion further comprises a digital (cascaded integrator-comb (CIC)) filter for (i) receiving the output audio samples at the desirable output rate and (ii) up-converting the output audio sample to an intermediate sample rate.

13. The DAC of claim 12 , wherein the digital processing portion further comprises a modulator mapper configured to receive the output audio samples at the intermediate sample rate, the modulator mapper being configured to reduce a noise level of the output audio samples, the modulator mapper producing a quantized output.

14. The DAC of claim 13 , wherein the digital processing portion further comprises a parallel to serial converter configured to (i) receive the quantized output, (ii) produce a serialized output therefrom, and (iii) provide the serialized output to the analog processing portion.

15. The DAC of claim 13 , wherein the fractional value is computed each period of the system clock.

16. The DAC of claim 15 , wherein the system clock has a higher rate than the input sample rate.

17. A method for converting digital audio data having a predetermined input sample rate to analog samples in a digital to analog converter (DAC), the method comprising:

receiving timing information representative of a time base of audio input data, the audio input data having a predetermined input sample rate;

producing an input sample rate value based upon the received timing information, the input sample rate value being representative of the predetermined input sample rate and a desirable output sample rate; and

rate converting the audio input data based upon a system clock, the rate converting producing output samples in accordance with the input sample rate value, the output samples being output at the desirable output sample rate;

wherein the input sample rate is independent of the system clock.

18. The method of claim 17 , wherein the rate converting is asynchronous.

19. The method of claim 17 , wherein the input sample rate value is a fractional value having ranges from −2 17 to 2 17 .

20. An apparatus configured for converting digital audio data having a predetermined input sample rate to analog samples in a digital to analog converter (DAC), the apparatus comprising:

means for receiving timing information representative of a time base of audio input data, the audio input data having a predetermined input sample rate;

means for producing an input sample rate value based upon the received timing information, the input sample rate value being representative of the predetermined input sample rate and a desirable output sample rate; and

means for rate converting the audio input data based upon a system clock, the rate converting producing output samples in accordance with the input sample rate value, the output samples being output at the desirable output sample rate;

wherein the input sample rate is independent of the system clock.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0097. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048555/0510 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0097 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 3, 2004
From: MILLER, KEVIN LEE; KLINGLER, KEITH LARELL; SCHONER, BRIAN FRANCIS
To: BROADCOM CORPORATION
Reel/Frame 015138/0632 →