Copper interconnects

1. A semiconductor device, comprising:

a semiconductor substrate;

a first metal layer formed overlying the semiconductor substrate;

a composite etch stop layer, comprising a first etch stop layer overlying a second etch stop layer, formed overlying the first metal layer and the semiconductor substrate;

a dielectric layer formed overlying the etch stop layer; and

a second metal layer penetrating the dielectric layer and the etch stop layer and electrically connected to the first metal layer;

wherein, the etch stop layer has a dielectric constant smaller than 3.5;

wherein, the dielectric layer has a dielectric constant smaller than 3.0;

wherein the dielectric layer has a tensile stress approximating to the compressive stress of the etch stop layer;

wherein the first etch stop layer is a SiCO film, and the second etch stop layer is a SiCO film;

wherein a first etching selectivity S 1 of the first etch stop layer to the dielectric layer, and a second etching selectivity S 2 of the second etch stop layer to the dielectric layer satisfy the formula: S 1 ≠S 2 .

2. The semiconductor device of claim 1 , wherein the etch stop layer has a compressive stress of 0˜1×10 9 dynes/cm 2 .

3. The semiconductor device of claim 1 , wherein the dielectric layer has a film hardness greater than 0.2 GPa and an elastic modulus greater than 5 GPa.

4. The semiconductor device of claim 1 , wherein S 1 and S 2 satisfy the formula: 0<S 1 <S 2 .

5. The semiconductor device of claim 1 , wherein a first thickness T 1 of the first etch stop layer and a second thickness T 2 of the second etch stop layer satisfy the formula: T 2 <(T 1 +T 2 )/3.

6. A fabrication method for a semiconductor device, comprising the steps of:

providing a semiconductor substrate having a first metal layer;

forming an etch stop layer overlying the first metal layer and the semiconductor substrate, wherein the etch stop layer has a dielectric constant smaller than 3.5;

forming a dielectric layer overlying the etch stop layer, wherein the dielectric layer has a dielectric constant smaller than 3.0;

forming an opening which penetrates the dielectric layer and the etch stop layer and exposes the first metal layer; and

forming a second metal layer in the opening, in which the second metal layer is electrically connected to the first metal layer, wherein the etch stop layer is a SiOC layer, and forming the etch stop layer is by a plasma enhanced chemical vapor deposition having:

SiH—(CH 3 ) 3 with a flow rate of 50˜300 sccm;

CO 2 with a flow rate of 300˜500 sccm;

a process temperature of 350˜400° C.;

a process pressure of 8˜10 Torr;

a high-frequency (HF) RF power of 300˜500 W; and

a low-frequency (LF) RF power of 60˜200 W.