Method for monitoring a set of semaphore registers using a limited-width test bus
View Patent ↗Certain embodiments of the invention may be found in a method and system for monitoring a set of semaphore registers using a limited-width test bus. Each semaphore register represents a separate hardware resource. The bits in a semaphore register are monitored jointly to determine whether the hardware resource it represents is in use by a software thread. The bits in the same register bit location of all the semaphore registers are monitored jointly to determine the ID number of the software thread currently using the hardware resource. The limited-width test bus comprises of bit lines representing each semaphore registers and bit lines representing the contents of the semaphore registers. Semaphore protocol steps are used in addition to changes monitored by the limited-width test bus to determine current usage of each hardware resource and to identify the ID number of the software thread using a hardware resource.
1. A method for sharing hardware resources in a digital system, the method comprising:
determining whether a hardware resource is in use by monitoring contents of at least one of a plurality of semaphore registers;
accessing said monitored contents of said plurality of semaphore registers by using a limited-width test bus whose bus width contains less than a number of bits needed to individually address each of said plurality of semaphore registers; and
XORing corresponding register bit locations in each one of said plurality of semaphore registers.
2. A method for sharing hardware resources in a digital system, the method comprising:
determining whether a hardware resource is in use by monitoring contents of at least one of a plurality of semaphore registers;
accessing said monitored contents of said plurality of semaphore registers by using a limited-width test bus whose bus width contains less than a number of bits needed to individually address each of said plurality of semaphore registers;
XORing corresponding register bit locations in each one of said plurality of semaphore registers; and
addressing each one of said register bit locations by coupling at least one XOR gate utilized for said XORing to a bit line in said limited-width test bus.
3. A method for sharing hardware resources in a digital system, the method comprising:
arranging a plurality of semaphore registers into a plurality of semaphore register blocks;
selecting one of said plurality of semaphore register blocks to be accessed by a limited-width test bus; and
determining a software thread identifier by XORing corresponding register bit locations in each one of said plurality of semaphore registers.
4. A system for sharing hardware resources in a digital system, the system comprising:
a plurality of hardware resources;
a plurality of semaphore registers coupled to said plurality of hardware resources; and
a limited-width test bus coupled to said plurality of semaphore registers, wherein said limited-width test bus contains less than a number of bits needed to individually address each of said plurality of semaphore registers and corresponding register bit locations in each one of said plurality of semaphore registers are coupled to an XOR gate.
5. A system for sharing hardware resources in a digital system, the system comprising:
a plurality of hardware resources;
a plurality of semaphore registers coupled to said plurality of hardware resources; and
a limited-width test bus coupled to said plurality of semaphore registers, wherein said limited-width test bus contains less than a number of bits needed to individually address each of said plurality of semaphore registers, corresponding register bit locations in each one of said plurality of semaphore registers are coupled to an XOR gate, and each said XOR gate is coupled to a bit line in said limited-width test bus.