Fin semiconductor device and method for fabricating the same

1. A semiconductor device comprising:

a projecting second semiconductor layer which is formed on a first semiconductor layer;

third and fourth semiconductor layers which are formed on the first semiconductor layer to be in contact with the second semiconductor layer and oppose each other via the second semiconductor layer;

a gate electrode which is in contact with the second semiconductor layer with a gate insulating film interposed there between and forms a channel in the second semiconductor layer; and

an insulating film which is formed in the first semiconductor layer located immediately under to third and fourth semiconductor layers, the third and fourth semiconductor layers being isolated from the first semiconductor layer by the insulating film, the second semiconductor layer being in contact with a region included in the first semiconductor layer and surrounded by the insulating film

wherein the insulating film is formed in the first semiconductor layer to surround a region located immediately under the second semiconductor layer.

2. The device according to claim 1 , wherein the gate electrode is formed so its ends oppose each other via the second semiconductor layer in a direction perpendicular to a direction in which the third and fourth semiconductor layers oppose each other.

3. The device according to claim 1 , further comprising a cell capacitor which is formed on the first semiconductor layer and whose storage node electrode is connected to one of the third and fourth semiconductor layers.

4. The device according to claim 3 , wherein the cell capacitor comprises a trench which is formed in the first semiconductor layer, the storage node electrode which fills the trench with a capacitor insulating film interposed therebetween, and a plate electrode which is formed in a region around the trench in the first semiconductor layer.

5. A semiconductor device comprising:

an insulating film formed on a first semiconductor layer;

a projecting second semiconductor layer which is formed on the insulating film;

third and fourth semiconductor layers which are formed on the insulating film to be in contact with the second semiconductor layer and oppose each other via the second semiconductor layer;

a gate electrode which is in contact with the second semiconductor layer with a gate insulating film interposed therebetween and forms a channel in the second semiconductor layer; and

a connection region which is formed immediately under the second semiconductor layer to electrically connect the first semiconductor layer and the second semiconductor layer;

wherein the connection region is isolated from the third and fourth semiconductor layers by the insulating film.

6. The device according to claim 5 , wherein in the connection region, the insulating film in a partial region immediately under the second semiconductor layer is removed, and a fifth semiconductor layer is formed in the region where the insulating film is removed.

7. The device according to claim 5 , wherein the third and fourth semiconductor layers are isolated from the first semiconductor layer by the insulating film.

8. The device according to claim 5 , wherein the gate electrode is formed so its ends oppose each other via the second semiconductor layer in a direction perpendicular to a direction in which the third and fourth semiconductor layers oppose each other.

9. The device according to claim 5 , further comprising a cell capacitor which is formed on the first semiconductor layer and whose storage node electrode is connected to one of the third and fourth semiconductor layers.

10. The device according to claim 9 , wherein the cell capacitor comprises a trench which is formed in the first semiconductor layer, the storage node electrode which fills the trench via a capacitor insulating film, and a plate electrode which is formed in a region around the trench in the first semiconductor layer.