Memory expansion and integrated circuit stacking system and method
View Patent ↗The present invention stacks integrated circuits (ICs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance. In a preferred embodiment of the memory addressing system, a high speed switching system selects a data line associated with each level of a stacked module to reduce the loading effect upon data signals in memory access.
1. A high-density circuit module comprising:
a first CSP having an upper and a lower major surface and a set of CSP contacts along the lower major surface;
a second CSP having first and second lateral edges and upper and lower major surfaces and a set of CSP contacts along the lower major surface, the first and second lateral edges delineating an extent of the upper major surface of the second CSP;
a form standard that is provided as a rigid mandrel and that is initially disposed above the upper surface of the second CSP, the form standard defining a standard sized form and including a thermally conductive material; and
a flex circuit that is at least partially disposed about the form standard subsequent to the form standard being disposed above the upper surface of the second CSP, the form standard defining a cross-sectional shape of the flex circuit.
2. A memory access system comprising:
a memory expansion board;
a high-density circuit module devised in accordance with claim 1 , the high-density circuit module being mounted on the memory expansion board;
a switching multiplexer mounted on the memory expansion board, the switching multiplexer for switching data lines between the first and second integrated circuits; and
a decode logic circuit for decoding chip selection signals from a control circuit and providing a switching multiplexer control signal.
3. A memory access system comprising:
a high-density circuit module devised in accordance with claim 1 ;
a switch for connecting a datapath to one of the plural integrated circuits of the high-density circuit module;
a decode logic for generating a control signal that causes the switch to connect the datapath to one of the plural integrated circuits in response to a combination signal comprised of a clock signal and a chip select signal.
4. A memory access system comprising:
plural memory expansion boards each populated with plural high-density circuit modules, each of which plural high-density circuit modules being devised in accordance with claim 1 ;
plural multiplexers mounted upon each of the plural memory expansion boards, the plural multiplexers for making connections between a datapath and single ones of the plural integrated circuits comprising the high-density circuit modules;
decode logic on each of the plural memory expansion boards, the decode logic for generating a control signal in response to a combination signal comprised of a clock signal and a chip select signal, the control signal causing at least one of the plural multiplexers to connect a particular datapath to a particular one of the plural integrated circuits.
5. A memory access system comprising:
a memory board having a board memory signal data connection that provides a connection for memory signals between a plurality of integrated circuits mounted on the memory board and memory control circuitry;
a high-density circuit module comprised of first, second, third, and fourth individual integrated circuits, the high-density circuit module being mounted on the memory board and devised in accordance with claim 1 ;
a switching multiplexer mounted on the memory board, the switching multiplexer having a set of plural input data connections, individual ones of the plural input data connections connected to provide individual data connections between each of the first, second, third, and fourth individual integrated circuits and the switching multiplexer; and
a decode logic circuit for decoding chip selection signals from a control circuit and providing a switching multiplexer control signal.
6. A memory access system comprising:
X memory expansion boards each populated with Y high-density circuit modules devised in accordance with claim 1 , each of which Y high-density circuit modules being comprised of Z individual integrated circuits;
plural multiplexers mounted upon each of the X memory expansion boards, the plural multiplexers each for selectively making connections between a datapath and single ones of the Z integrated circuits comprising each of the y high-density circuit modules;
decode logic on each of the plural memory expansion boards, the decode logic for generating a control signal in response to a combination signal comprised of a clock signal and a chip select signal, the control signal causing at least one of the plural multiplexers to connect a particular datapath to a particular one of the Z integrated circuits.
7. The memory access system of claim 3 in which the plural integrated circuits of the high-density circuit module number four.
8. The memory access system of claim 4 in which the multiplexers arc FET multiplexers.
9. The memory access system of claim 4 in which the plural high-density circuit modules are comprised of four integrated circuits.
10. The memory access system of claim 4 in which the plural high-density circuit modules arc comprised from two integrated circuits.
11. The memory access system of claim 5 in which the switching multiplexer further comprises an output data connection connected to the board signal memory data connection.
12. The memory access system of claim 5 in which the decode logic circuit is mounted on the memory board.
13. The memory access system of claim 6 in which the multiplexers are FET multiplexers.
14. The memory access system of claim 6 in which Z equals 4.
15. The memory access system of claim 6 in which Z equals 2.
16. The memory access system of claim 11 in which the switching multiplexer provides selective individual connection between the board signal memory data connection and the first, second, third, and fourth individual integrated circuits.
17. The memory access system of claim 16 in which the individual connection between the board signal memory data connection and the first, second, third, and fourth individual integrated circuits occurs in response to the switching multiplexer control signal from the decode logic circuit.