IP Library Granted Patent US 7,234,007
Granted Patent B2
US 7,234,007 · App. 10/811,126 · Granted Jun 19, 2007

Adjustable elasticity FIFO buffer have a number of storage cells equal to a frequency offset times a number of data units in a data stream

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Quick Facts
Patent No.
US 7,234,007
App. No.
10/811,126
Granted
Jun 19, 2007
Kind
B2
Abstract

A method of processing a data stream through a buffer is performed in accordance with a write clock and a read clock. The buffer has a plurality of sequentially numbered storage cells. The method includes the steps of selecting an initial preload value, with the selecting step including determining a product of the maximum frequency offset between the write and read clocks, and a maximum time between arbitrary symbols in the data stream. The storage cells then receive data units in response to a write pointer. Data units are then provided from the storage cells in response to a read pointer.

Claims (9)

1. A buffer for allowing influx and outflow of data in a data stream, said buffer comprising:

a write pointer for writing data in accordance with a frequency of a write clock;

a read pointer for reading data in accordance with a frequency of a read clock;

a number of storage cells, said number of storage cells being substantially equal to a product of a maximum frequency offset between the write clock and the read clock, and a maximum number of data units in a data interval between arbitrary symbols in the data stream.

2. A buffer as recited in claim 1 , wherein said arbitrary symbols comprise ordered sets.

3. A buffer as recited in claim 1 , wherein said arbitrary symbols comprise skip symbols.

4. A buffer as recited in claim 1 , wherein said arbitrary symbols comprise PCI express skip symbols.

5. A buffer as recited in claim 1 , wherein the data stream comprises a continuous data stream having datagrams embedded therein, and wherein the arbitrary symbols comprise skip symbols disposed within the continuous data stream.

6. A buffer as recited in claim 1 , wherein said buffer is configured to allow influx and outflow of data in a data stream, wherein said data stream is a continuous data stream including embedded datagrams having no inter-packet gap.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0097. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048555/0510 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0097 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 29, 2004
From: CASTELLANO, ANDREW; YANG, PINGHUA (PETER)
To: BROADCOM CORPORATION
Reel/Frame 015158/0287 →