Method and system for controlling MRAM write current to reduce power consumption
View Patent ↗In a method and system for reducing power consumed by a magnetic memory, magnetic memory cells are coupled to a bit line and are associated with a plurality of digit lines. A bit line current is provided in the bit line. Digit currents are provided in parallel in the digit lines at substantially the same time as the bit line current. The digit and bit line currents allow the magnetic memory cells to be written to a plurality of states in parallel.
1. A method for programming a plurality of magnetic memory cells, the plurality of magnetic memory cells being coupled to a bit line, the plurality of magnetic memory cells being associated with a plurality of digit lines, the method comprising the steps of:
(a) providing a predetermined bit line current I B in the bit line at a predetermined bit line voltage V B ; and
(b) providing a plurality of predetermined digit currents I D in parallel in the plurality of digit lines at a predetermined digit line voltage V D for the plurality of magnetic memory cells at substantially the same time as the bit line current I B , the plurality of digit currents and the bit line current allowing the plurality of magnetic memory cells to be written to a plurality of states in parallel, wherein the total power supplied to the plurality of magnetic memory cells during writing is I B V B +NI D V D , where N is the number of digit lines.
2. The method of claim 1 wherein the bit line current is applied for a first predetermined time and the plurality of digit currents is provided for a second predetermined time.
3. The method of claim 2 wherein the first predetermined time is two nanoseconds.
4. The method of claim 3 wherein the second predetermined time is 1.6 nanoseconds.
5. A magnetic memory comprising:
a plurality of magnetic memory cells
a bit line, the plurality of magnetic memory cells being coupled to the bit line;
a plurality of digit lines, the plurality of magnetic memory cells being associated with the plurality of digit lines;
at least one write circuit configured to provide a predetermined bit line current I B in the bit line at a predetermined bit line voltage V B and to provide a plurality of predetermined digit currents I D in parallel in the plurality of digit lines at a predetermined digit line voltage V D in parallel at substantially the same time as the bit line current I B , the plurality of digit currents and the bit line current allowing the plurality of magnetic memory cells to be written to a plurality of states in parallel, wherein the total power supplied to the plurality of magnetic memory cells during writing is I B V B +NI B V D , where N is the number of digit lines.
6. The magnetic memory of claim 5 wherein the bit line current is applied for a first predetermined time and the plurality of digit currents is provided for a second predetermined time.
7. The magnetic memory of claim 6 wherein the first predetermined time is two nanoseconds.
8. The magnetic memory of claim 7 wherein the second predetermined time is 1.6 nanoseconds.