Semiconductor integrated circuit and nonvolatile memory element
View Patent ↗0 Owing to the above, even with the single-layer gate process such as single-layer polysilicon gate process, it is possible to obtain a semiconductor integrated circuit such as system LSI in which a nonvolatile memory which is excellent in data retention capability is merged and packaged with a DRAM etc. Further, since the nonvolatile memory of high reliability can be formed without adding any step to a related art manufacturing process, such as a standard CMOS manufacturing process, the present invention may be readily applied to an LSI in which the nonvolatile memory and a logic LSI, or the nonvolatile memory and a DRAM are merged and packaged on an identical semiconductor substrate. Accordingly, a system LSI in which a flash memory is merged and packaged can be provided without increasing the cost of manufacture.
1. A semiconductor integrated circuit device formed on a substrate by a single layer polycrystalline silicon process, comprising:
an internal circuit which includes P-channel transistors and N-channel transistors, each of which has a gate electrode of a single polycrystalline silicon layer on the substrate;
a first memory which includes a plurality of memory cells, each memory cell having a floating gate of the single polycrystalline silicon layer and a control gate of a semiconductor region in the substrate; and
a second memory coupled to receive data stored in the first memory.
2. A semiconductor integrated circuit device according to claim 1 , wherein the P-channel transistors and N-channel transistors in the internal circuit have gate insulating films thicker than that of the memory cells.
3. A semiconductor integrated circuit device according to claim 2 , further comprising:
an external input/output circuit coupled to the internal circuit,
wherein the external input/output circuit includes P-channel transistors and N-channel transistors having gate insulating films whose thickness are substantially equal to that of the gate insulating films of the memory cells.
4. A semiconductor integrated circuit device according to claim 1 , wherein the data stored in the first memory are read out and stored into the second memory in response to a power-on of the semiconductor integrated circuit device.
5. A semiconductor integrated circuit device according to claim 4 , wherein the power-on includes a reset operation of the semiconductor integrated circuit device.
6. A semiconductor integrated circuit device formed on a semiconductor substrate, comprising:
a memory cell including a pair of electrically programmable nonvolatile memory elements, each memory element including a MIS transistor having a source, a drain, a floating gate and a control gate, formed in a p-type well region and a n-type well region adjacent to, and isolated from the p-type well region on a semiconductor substrate, wherein:
the source and the drain of each memory element are formed in first and second n-type diffusion regions of the p-type well region;
the floating gate of each memory element is formed of a conductive layer arranged over a channel defined between the source and the drain, via a first gate insulating film; and
the control gate of each memory element is formed of the n-well region on the semiconductor substrate, arranged under a portion of the conductive layer extended from the floating gate, via a second gate insulating film;
a word line coupled to control gates of the pair of electrically programmable nonvolatile memory elements; and
a pair of complementary data lines arranged in perpendicular with the word line and coupled to drains of the pair of electrically programmable nonvolatile memory elements.
7. A semiconductor integrated circuit device according to claim 6 , further comprising:
a volatile storage circuit in which control information stored in the memory cell is to be stored; and
a signal line arranged in parallel to the word line, which transmit commands in parallel for an operation of reading the control information from the memory cell and an operation for writing the control information into the memory cell.
8. A semiconductor integrated circuit device according to claim 6 , wherein the pair of electrically programmable nonvolatile memory elements are coupled in a differential form.
9. A semiconductor integrated circuit device according to claim 6 , further comprising a sense amplifier coupled to complementary data lines for differentially amplifying information read out on the pair of complementary data lines in accordance with mutually different logical states of the pair of electrically programmable nonvolatile memory elements.
10. A semiconductor integrated circuit device formed on a semiconductor substrate, comprising:
a memory cell including a pair of electrically programmable nonvolatile memory elements, each memory element including a MIS transistor having a source, a drain, a floating gate and a control gate, formed in a first well region exhibiting a first conductivity and a second well region exhibiting a second conductivity adjacent to, and isolated from the first well region on a semiconductor substrate, wherein:
the source and the drain of each memory element are formed in first and second diffusion regions exhibiting a second conductivity within the first well region;
the floating gate of each memory element is formed of a conductive layer arranged over a channel defined between the source and the drain, via a first gate insulating film; and
the control gate of each memory element is formed of the second well region on the semiconductor substrate, arranged under a portion of the conductive layer extended from the floating gate, via a second gate insulating film;
a word line coupled to control gates of the pair of electrically programmable nonvolatile memory elements; and
a pair of complementary data lines arranged in perpendicular with the word line and coupled to drains of the pair of electrically programmable nonvolatile memory elements.
11. A semiconductor integrated circuit device according to claim 10 , further comprising:
a volatile storage circuit in which control information stored in the memory cell is to be stored; and
a signal line arranged in parallel to the word line, which transmit commands in parallel for an operation of reading the control information from the memory cell and an operation for writing the control information into the memory cell.
12. A semiconductor integrated circuit device according to claim 10 , wherein the pair of electrically programmable nonvolatile memory elements are coupled in a differential form.
13. A semiconductor integrated circuit device according to claim 10 , further comprising a sense amplifier coupled to complementary data lines for differentially amplifying information read out on the pair of complementary data lines in accordance with mutually different logical states of the pair of electrically programmable nonvolatile memory elements.