IP Library Granted Patent US 7,868,472
Granted Patent B2
US 7,868,472 · App. 10/820,484 · Granted Jan 11, 2011

Thermal dissipation in integrated circuit systems

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,868,472
App. No.
10/820,484
Granted
Jan 11, 2011
Kind
B2
Abstract

Integrated circuit systems with thermal dissipation enhancement features are described. In one aspect, an integrated circuit system includes a die incorporating an integrated circuit. The die has a top side and a bottom side. The top side supports an electrical signal communication metallization and a top side thermal dissipation metallization. The bottom side supports a bottom side thermal dissipation metallization.

Claims (25)

1. An integrated circuit system, comprising:

a die incorporating an integrated circuit and having a top side and a bottom side, the top side supporting an electrical signal communication metallization and a top side thermal dissipation metallization, and the bottom side supporting a bottom side thermal dissipation metallization.

2. The system of claim 1 , wherein the electrical signal communication metallization comprises a plurality of exposed bonding elements on the top side of the die.

3. The system of claim 2 , wherein the bonding elements are contained in a peripheral region on the top side of the die.

4. The system of claim 3 , wherein the top side thermal dissipation metallization is contained in a central region on the top side of the die.

5. The system of claim 4 , wherein the top side thermal dissipation metallization is surrounded by the plurality of bonding elements.

6. The system of claim 1 , wherein the electrical signal communication metallization surrounds the top side thermal dissipation metallization.

7. The system of claim 1 , wherein the top side thermal dissipation metallization comprises a patterned metal layer.

8. The system of claim 7 , wherein the patterned metal layer comprises at least one through-hole.

9. The system of claim 8 , wherein the patterned metal layer comprises an array of through-holes.

10. The system of claim 1 , further comprising a package comprising a top heat spreader metallurgically bonded to the top side thermal dissipation metallization of the die.

11. The system of claim 10 , wherein the integrated circuit is connected electrically to the top side heat spreader by an electrical path extending through the top side thermal dissipation metallization.

12. The system of claim 10 , wherein the package further comprises an electrical interface and a substrate containing a wiring interconnection between the electrical signal communication metallization and the electrical interface.

13. The system of claim 12 , wherein the top heat spreader is mounted on the substrate and forms a lid of the package covering the top side of the die.

14. The system of claim 10 , wherein the package further comprises a bottom heat spreader metallurgically bonded to the bottom side thermal dissipation metallization of the die.

15. A method of making an integrated circuit system, comprising:

forming on a top side of a substrate multiple die regions each having a top side supporting an exposed electrical signal communication metallization and an exposed top side thermal dissipation metallization;

forming on a bottom side of the substrate an exposed bottom side thermal dissipation metallization for each die region; and

singulating the die regions to form respective integrated circuit dice.

16. The method of claim 15 , wherein, in each die region, the electrical signal communication metallization surrounds the top side thermal dissipation metallization.

17. The method of claim 15 , wherein each top side thermal dissipation metallization comprises an exposed metal layer with an array of through-holes.

18. The method of claim 15 , further comprising mounting each singulated die in a respective package having a top heat spreader, wherein mounting a singulated die comprises metallurgically bonding the top heat spreader of a package to the top side thermal dissipation metallization of the singulated die.

19. The method of claim 18 , wherein the package additionally includes a substrate and mounting the singulated die further comprises mounting the package substrate to the bottom side thermal dissipation metallization of the singulated die.

20. The method of claim 18 , wherein the top heat spreader is mounted on the substrate and forms a lid of the package, and further comprising encapsulating the die within the package with an encapsulating material.

21. The system of claim 1 , wherein the electrical signal communication metallization is free of any direct electrical connection to the top side thermal dissipation metallization on the top side of the die.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 017206 FRAME: 0666. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 6, 2016
From: AGILENT TECHNOLOGIES, INC.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 038632/0662 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 20, 2014
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: III HOLDINGS 1, LLC
Reel/Frame 032932/0719 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2006
From: AGILENT TECHNOLOGIES, INC.
To: AVAGO TECHNOLOGIES GENERAL IP PTE. LTD.
Reel/Frame 017206/0666 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 19, 2004
From: KELLY, MICHAEL G.
To: AGILENT TECHNOLOGIES, INC.
Reel/Frame 015075/0082 →