Methods and structures for planar and multiple-gate transistors formed on SOI
View Patent ↗A semiconductor device includes an insulator layer, a semiconductor layer, a first transistor, and a second transistor. The semiconductor layer is overlying the insulator layer. A first portion of the semiconductor layer has a first thickness. A second portion of the semiconductor layer has a second thickness. The second thickness is larger than the first thickness. The first transistor has a first active region formed from the first portion of the semiconductor layer. The second transistor has a second active region formed from the second portion of the semiconductor layer. The first transistor may be a planar transistor and the second transistor may be a multiple-gate transistor, for example.
1. A semiconductor device comprising:
an insulator layer;
a planar transistor formed on a first portion of a semiconductor layer, the first portion of the semiconductor layer overlying the insulator layer, and the first portion of the semiconductor layer having a first thickness;
a multiple-gate transistor formed on a second portion of the semiconductor layer, the second portion of the semiconductor layer overlying the insulator layer, the second portion of the semiconductor layer having a second thickness, and the second thickness being larger than the first thickness; and
the planar transistor comprising:
a planar channel formed from the first portion of the semiconductor layer;
a gate dielectric having vertical portions on opposite sidewalls of the planar channel and a horizontal portion on a top surface of the planar channel;
a gate electrode overlying the gate dielectric, wherein the gate electrode has vertical portions on the vertical portions of the gate dielectric and a horizontal portion on the horizontal portion of the gate dielectric; and
source and drain regions formed in the first portion of the semiconductor layer oppositely adjacent the gate electrode.
2. The semiconductor device of claim 1 , wherein the first thickness is less than about a half of a gate length of the planar transistor.
3. The semiconductor device of claim 2 , wherein the first thickness is less than about one-third of a gate length of the planar transistor.
4. The semiconductor device of claim 1 , wherein the first thickness is less than about 400 angstroms.
5. The semiconductor device of claim 1 , wherein the second thickness is greater than about 100 angstroms.
6. The semiconductor device of claim 1 , wherein the gate dielectric of the planar transistor comprises a material selected from a group consisting of silicon oxide, silicon oxynitride, high-k dielectric material, a dielectric with a relative permittivity larger than about 5, and combinations thereof.
7. The semiconductor device of claim 1 , wherein the gate electrode of the planar transistor comprises a material selected from a group consisting of a metal, a metallic nitride, a metallic suicide, poly-crystalline silicon, and combinations thereof.
8. The semiconductor device of claim 1 , wherein a gate dielectric of the multiple-gate transistor comprises a material selected from a group consisting of silicon oxide, silicon oxynitride, high-k dielectric material, a dielectric with a relative permittivity larger than about 5, and combinations thereof.
9. The semiconductor device of claim 1 , wherein a gate electrode of the multiple-gate transistor comprises a material selected from a group consisting of a metal, a metallic nitride, a metallic suicide, poly-crystalline silicon, and combinations thereof.
10. The semiconductor device of claim 1 , wherein corners of the semiconductor layer are rounded at edges of active regions of the planar and multiple-gate transistors.