Variable transconductance variable gain amplifier utilizing a degenerated differential pair
View Patent ↗Continuously tuning a transconductance. Coupling a degeneration resistance from a first source of a first transistor in a differential pair of transistors to a second source of a second transistor in the differential pair of transistors. Applying a second variable degeneration resistance in parallel to the first degeneration resistance in response to the application of a first variable control voltage. And applying a third variable degeneration resistance in parallel to the first degeneration resistance and the second degeneration resistance in response to the application of a second variable control voltage having a fixed voltage offset from the first variable control voltage.
1. A variable gain amplifier, comprising:
a first transistor and a second transistor coupled together differentially;
a plurality of degeneration resistance circuits, each having a switch responsive to a control voltage, coupled to said first transistor and said second transistor; and
means for varying the control voltage to stagger turn-on of said plurality of degeneration resistance circuits.
2. The amplifier of claim 1 , wherein each of said plurality of degeneration resistance circuits has an approximately equal resistance.
3. The amplifier of claim 2 , wherein each of said plurality of degeneration resistance circuits has a resistance, said resistance of a first degeneration resistance circuit being greater than said resistance of a second degeneration resistance circuit.
4. The amplifier of claim 2 , wherein said means for varying the control voltage includes a voltage offset ladder circuit.
5. The amplifier of claim 2 , wherein said first transistor and said second transistor are NMOS devices.
6. An integrated circuit, comprising:
a substrate; and
a variable gain amplifier, disposed on said substrate, including
a first transistor and a second transistor coupled together differentially,
a plurality of degeneration resistance circuits, each having a switch responsive to a voltage, coupled to said first transistor and said second transistor, and
a control circuit that varies the voltage to stagger turn-on of said plurality of degeneration resistance circuits.
7. The integrated circuit of claim 6 , further comprising:
a receiver, disposed on said substrate, that converts a received RF signal to an IF signal, and
wherein said variable gain amplifier amplifies the IF signal.
8. The integrated circuit of claim 7 , wherein the gain of said variable gain amplifier is responsive to a strength of the RF signal.
9. The integrated circuit of claim 7 , wherein each of said plurality of degeneration resistance circuits has an approximately equal resistance.
10. The integrated circuit of claim 7 , wherein each of said plurality of degeneration resistance circuits has a resistance, said resistance of a first degeneration resistance circuit being greater than said resistance of a second degeneration resistance circuit.
11. The integrated circuit of claim 7 , wherein said control circuit includes a voltage offset ladder circuit.
12. The integrated circuit of claim 7 , wherein said first transistor and said second transistor are NMOS devices.
13. A system for amplifying a signal, comprising:
a first transistor and a second transistor coupled together differentially,
a plurality of degeneration resistance circuits, each having a switch responsive to a first voltage, coupled to said first transistor and said second transistor; and
a control circuit that varies the first voltage to stagger turn-on of said plurality of degeneration resistance circuits.
14. The system of claim 13 , wherein the amplification of an input signal is proportional to a strength of the input signal.
15. The system of claim 13 , wherein the amplification of an input signal is proportional to a strength of a second signal.
16. The system of claim 15 , wherein the input signal is derived from the second signal.
17. The system of claim 13 , wherein each of said plurality of degeneration resistance circuits has an approximately equal resistance.
18. The system of claim 13 , wherein each of said plurality of degeneration resistance circuits has a resistance, said resistance of a first degeneration resistance circuit being greater than said resistance of a second degeneration resistance circuit.
19. The system of claim 13 , wherein said control circuit includes a voltage offset ladder circuit.
20. The system of claim 13 , wherein said first transistor and said second transistor are NMOS devices.