Erroneous operation preventing circuit of non-volatile memory device
View Patent ↗An erroneous operation preventing circuit of an electrically rewritable non-volatile memory device is for setting one or more operational modes of a plurality of operational modes including at least a first reading mode of reading out data from a memory array 4, a programming mode, an erasing mode and a second reading mode of reading out data not stored in the memory array 4, in accordance with an input control command, and for performing a predetermined process in the set operational modes. The erroneous operation preventing circuit comprises an operational mode enforcing circuit 2 a for setting the first reading mode regardless of the input of the control command, in a data protection status where the programming mode and the erasing mode are inhibited from being set in accordance with a control signal for protecting predetermined data.
1. An erroneous operation preventing circuit of an electrically rewritable non-volatile memory device which sets one or more of a plurality of operational modes including a first reading mode of reading out data from a memory array, a programming mode of writing data to the memory array, an erasing mode of erasing data from the memory array, and a second reading mode of reading out other data, in accordance with an input control command, and performing a predetermined process in the operational modes, the circuit comprising:
an operational mode enforcing circuit coupled to the memory array and configured to set the first reading mode regardless of the input control command, in a data protection status where the programming mode and the erasing mode are inhibited from being set in accordance with a control signal for protecting predetermined data in the memory array.
2. The erroneous operation preventing circuit according to claim 1 , further comprising a data protection area specifying unit configured to specify a data protection area such that the data protection status is valid only in the specified data protection area in the memory array,
wherein the operational mode enforcing circuit sets the first reading mode regardless of the input control command, when the data protection area is specified by an input address in the data protection status.
3. The erroneous operation preventing circuit according to claim 1 , wherein the operational mode enforcing circuit sets the operational mode in accordance with the input control command, in a status where the programming mode and the erasing mode are not inhibited from being set in accordance with the control signal.
4. The erroneous operation preventing circuit of according to claim 1 , wherein the control signal includes one or more control signals for data protection, a data-writing high voltage input signal, a data-erasing high voltage input signal and a data-writing/erasing high voltage input signal.
5. The erroneous operation preventing circuit according to claim 1 , wherein, in the data protection status, data input to the memory device is disabled and input of control commands is prevented.
6. An erroneous operation preventing circuit of an electrically rewritable non-volatile memory device which sets one or more of a plurality of operational modes including a first reading mode of reading out data from a memory array, a programming mode of writing data to the memory array, an erasing mode of erasing data from the memory array, and a second reading mode of reading out other data, in accordance with an input control command, and performing a predetermined process in the operational modes, the circuit comprising:
an operational mode enforcing circuit coupled to the memory array and configured to set enforcedly an associated control command input circuit which is coupled to the operational mode enforcing circuit to a level corresponding to the first reading mode regardless of an input level of the control command, in a data protection status where the programming mode and the erasing mode are inhibited from being set in accordance with a control signal for protecting predetermined data in the memory array.
7. The erroneous operation preventing circuit according to claim 6 , further comprising a data protection area specifying unit configured to specify a data protection area such that the data protection status is valid only in the specified data protection area in the memory array,
wherein the operational mode enforcing circuit enforcedly sets the control command input circuit to the level corresponding to the first reading mode regardless of the input level of the control command, when the data protection area is specified by an input address in the data protection status.
8. The erroneous operation preventing circuit according to claim 6 , wherein the operational mode enforcing circuit sets the control command input circuit to the level corresponding to the input level of the control command, in a status where the programming mode and the erasing mode are not inhibited from being set in accordance with the control signal.
9. The erroneous operation preventing circuit according to claim 6 , wherein the control signal includes one or more control signals for data protection, a data-writing high voltage input signal, a data-erasing high voltage input signal and a data-writing/erasing high voltage input signal.
10. The erroneous operation preventing circuit according to claim 6 , wherein, in the data protection status, data input to the memory device is disabled and input of control commands is prevented.