Apparatus and method for generating a cryptographic key schedule in a microprocessor
An apparatus and method for performing cryptographic operations. In one embodiment, an apparatus is provided for performing cryptographic operations. The apparatus includes fetch logic, keygen logic, and execution logic. The fetch logic is disposed within a microprocessor and receives cryptographic instruction single atomic cryptographic instruction as part of an instruction flow executing on the microprocessor. The cryptographic instruction single atomic cryptographic instruction prescribes one of the cryptographic operations, and also prescribes that a provided cryptographic key be expanded into a corresponding key schedule for employment during execution of the one of the cryptographic operations. The keygen logic is disposed within the microprocessor and is operatively coupled to the single atomic cryptographic instruction. The keygen logic directs the microprocessor to expand the provided cryptographic key into the corresponding key schedule. The execution logic is coupled to the keygen logic. The execution logic is disposed within the microprocessor and expands the provided cryptographic key into the corresponding key schedule.
1. An apparatus for performing cryptographic operations, comprising:
an x86-compatible microprocessor;
a control word, configured to prescribe that a provided cryptographic key be expanded into a corresponding key schedule for employment during execution of one of the cryptographic operations, wherein said control word is stored in memory, and wherein a memory location of said control word is prescribed by contents of a register that is referenced by a single atomic cryptographic instruction, wherein said single atomic cryptographic instruction is arranged according to the instruction format for execution on said x86-compatible microprocessor;
fetch logic, disposed within said x86-compatible microprocessor, configured to receive said single atomic cryptographic instruction as part of an instruction flow executing on said x86-compatible microprocessor, wherein said single atomic cryptographic instruction prescribes said one of the cryptographic operations, and wherein said single atomic cryptographic instruction references said control word;
translation logic, coupled to said fetch logic, configured to translate said single atomic cryptographic instruction into a sequence of micro instructions that directs said x86-compatible microprocessor to perform said one of the cryptographic operations;
keygen logic, disposed within said x86-compatible microprocessor and operatively coupled to said single atomic cryptographic instruction, configured to direct said x86-compatible microprocessor to expand said provided cryptographic key into said corresponding key schedule; and
execution logic, disposed within said x86-compatible microprocessor and operatively coupled to said keygen logic, configured to expand said provided cryptographic key into said corresponding key schedule, said execution logic comprising:
a cryptography unit, configured to execute a plurality of cryptographic rounds on each of a plurality of input text blocks to generate a corresponding each of a plurality of output text blocks, wherein said plurality of cryptographic rounds are prescribed by said control word.
2. The apparatus as recited in claim 1 , wherein said one of the cryptographic operations further comprises:
an encryption operation, said encryption operation comprising encryption of a plurality of plaintext blocks to generate a corresponding plurality of ciphertext blocks.
3. The apparatus as recited in claim 1 , wherein said one of the cryptographic operations further comprises:
a decryption operation, said decryption operation comprising decryption of a plurality of ciphertext blocks to generate a corresponding plurality of plaintext blocks.
4. The apparatus as recited in claim 1 , wherein said provided cryptographic key is stored in memory.
5. The apparatus as recited in claim 1 , wherein said corresponding key schedule comprises an expanded key schedule according to the Advanced Encryption Standard (AES) algorithm.
6. The apparatus as recited in claim 1 , wherein said keygen logic is configured to interpret a key generation field within said control word which is referenced by said single atomic cryptographic instruction.
7. The apparatus as recited in claim 1 , wherein said single atomic cryptographic instruction implicitly references a plurality of registers within said x86-compatible microprocessor.
8. The apparatus as recited in claim 7 , wherein said plurality of registers comprises:
a first register, wherein contents of said first register comprise a first pointer to a first memory address, said first memory address specifying a first location in memory for access of said plurality of input text blocks upon which said one of the cryptographic operations is to be accomplished.
9. The apparatus as recited in claim 7 , wherein said plurality of registers comprises:
a first register, wherein contents of said first register comprise a first pointer to a first memory address, said first memory address specifying a first location in memory for storage of said corresponding plurality of output text blocks.
10. The apparatus as recited in claim 7 , wherein said plurality of registers comprises:
a first register, wherein contents of said first register indicate a number of text blocks within said plurality of input text blocks.
11. The apparatus as recited in claim 7 , wherein said plurality of registers comprises:
a first register, wherein contents of said first register comprise a first pointer to a first memory address, said first memory address specifying a first location in memory for access of cryptographic key data for use in accomplishing said one of the cryptographic operations.
12. The apparatus as recited in claim 11 , wherein said cryptographic key data comprises said provided cryptographic key.
13. The apparatus as recited in claim 7 , wherein said plurality of registers comprises:
a first register, wherein contents of said first register comprise a first pointer to a first memory address, said first memory address specifying a first location in memory, said first location comprising an initialization vector location, contents of said initialization vector location comprising an initialization vector or initialization vector equivalent for use in accomplishing said one of the cryptographic operations.
14. The apparatus as recited in claim 7 , wherein said plurality of registers comprises:
a first register, wherein contents of said first register comprise a first pointer to a first memory address, said first memory address specifying a first location in memory for access of said control word for use in accomplishing said one of the cryptographic operations, wherein said control word prescribes cryptographic parameters for said one of the cryptographic operations, and wherein said control word comprises:
a keygen field, configured to specify that said provided cryptographic key be expanded into said corresponding key schedule.
15. An apparatus for performing cryptographic operations, comprising:
an x86-compatible microprocessor;
a control word, configured to prescribe that a cryptographic key be expanded into a corresponding key schedule for employment when executing one of the cryptographic operations, wherein said control word is stored in memory, and wherein a memory location of said control word is prescribed by contents of a register that is referenced by a single atomic cryptographic instruction, wherein said single atomic cryptographic instruction is arranged according to the instruction format for execution on said x86-compatible microprocessor;
a cryptography unit disposed within execution logic in said x86-compatible microprocessor, configured to execute said one of the cryptographic operations responsive to receipt by said x86-compatible microprocessor of said single atomic cryptographic instruction within an instruction flow that prescribes said one of the cryptographic operations, wherein said single atomic cryptographic instruction is fetched from memory by fetch logic in said x86-compatible microprocessor, and wherein translation logic in said x86-compatible microprocessor translates said single atomic cryptographic instruction into a sequence of micro instructions that directs said x86-compatible microprocessor to perform said one of the cryptographic operations; and
keygen logic, operatively coupled to said cryptography unit, configured to direct said x86-compatible microprocessor to perform said one of the cryptographic operations and to expand said cryptographic key into said corresponding key schedule.
16. The apparatus as recited in claim 15 , wherein said cryptographic key is stored in memory.
17. The apparatus as recited in claim 15 , wherein said corresponding key schedule comprises an expanded key schedule according to the Advanced Encryption Standard (AES) algorithm.
18. The apparatus as recited in claim 15 , wherein said keygen logic is configured to interpret a key generation field within said control word which is referenced by said single atomic cryptographic instruction.
19. A method for performing cryptographic operations, the method comprising:
via fetch logic disposed within an x86-compatible microprocessor, fetching a single atomic cryptographic instruction from memory that prescribes one of a plurality of cryptographic operations, and via translation logic disposed within the x86-compatible microprocessor, translating the single atomic cryptographic instruction into a sequence of micro instructions that direct the x86-compatible microprocessor to perform the one of the plurality of cryptographic operations, wherein the single atomic cryptographic instruction is arranged according to the instruction format for execution on the x86-compatible microprocessor;
via a field within a control word that is referenced by the single atomic cryptographic instruction, specifying expansion of a cryptographic key into a corresponding key schedule for employment during execution of the one of a plurality of cryptographic operations; and
via a cryptography unit disposed within execution logic in the x86-compatible microprocessor, expanding the cryptographic key into the corresponding key schedule.
20. The method as recited in claim 19 , wherein said expanding comprises:
loading the cryptographic key from memory.
21. The method as recited in claim 19 , wherein the corresponding key schedule comprises an expanded key schedule according to the Advanced Encryption Standard (AES) algorithm.