Method for forming a gate electrode having a metal
View Patent ↗One embodiment forms a gate dielectric layer over a substrate and then selectively deposits a first metal layer over portions of the gate dielectric layer in which a first device type will be formed. A second metal layer, different from the first metal layer, is formed over exposed portions of the gate dielectric layer in which a second device type will be formed. Each of the first and second device types will have different work functions because each will include a different metal in direct contact with the gate dielectric. In one embodiment, the selective deposition of the first metal layer is performed by ALD and with the use of an inhibitor layer which is selectively formed over the gate dielectric layer such that the first metal layer may be selectively deposited on only those portions of the gate dielectric layer which are not covered by the inhibitor layer.
1. A method of making transistors, the method comprising:
selectively depositing a first metal layer on a gate dielectric of a first region of a wafer and not on a gate dielectric of a second region of the wafer;
depositing a second metal layer over the gate dielectric of the second region;
forming a first gate electrode stack for a first transistor in the first region, the first gate electrode stack including a structure formed from the first metal layer;
forming a second gate electrode stack for a second transistor in the second region, the second gate electrode stack including a structure formed from the second metal layer,
wherein the method further comprises:
forming an inhibitor on the gate dielectric of the second region, wherein the inhibitor inhibits the deposition of the first metal layer on the gate dielectric of the second region.
2. The method of clam 1 wherein the first transistor is a PMOS transistor and the second transistor is an NMOS transistor.
3. The method of claim 1 wherein the first transistor is an NMOS transistor and the second transistor is a PMOS transistor.
4. The method of claim 1 wherein:
the depositing the second metal layer further comprises depositing the second metal layer over the fast metal layer in the first region;
wherein the first gate electrode stack includes a structure formed from the second metal layer over the first metal layer.
5. The method of claim 1 wherein the inhibitor inhibits by blocking nucleation sites on the gate dielectric of the second region.
6. The method of claim 1 wherein the inhibitor is characterized as a self assembling monolayer.
7. The method of claim 1 wherein the inhibitor includes an organosilane.
8. The method of claim 1 wherein the inhibitor includes a methyl group.
9. The method of claim 1 wherein the inhibitor includes a methacrylate based polymer.
10. The method of claim 1 wherein the inhibitor includes a photodefinable polymer.
11. The method of claim 1 wherein the first metal layer includes one of tantalum silicon nitride, tantalum carbide, a metal boride, a metal silicon nitride, and a metal carbide.
12. The method of claim 1 wherein the first metal layer includes one of titanium nitride, iridium, iridium oxide, ruthenium, ruthenium oxide, and tantalum nitride.
13. The method of claim 1 wherein the first metal layer is selectively deposited using an atomic layer deposition (ALD) process.
14. The method of claim 1 wherein the first metal layer is selectively deposited using a chemical vapor deposition (CVD) process.
15. The method of claim 1 further comprising:
forming a polysilicon layer over the first metal layer in the first region and a polysilicon layer over the second metal layer in the second region;
wherein the first gate electrode stack includes a structure formed from the polysilicon layer over the first metal layer in the first region;
wherein the second gate electrode stack includes a structure formed from the polysilicon layer over the second metal layer in the second region.
16. The method of claim 1 wherein the first metal layer has a first work function and the second metal layer has a second work function, die first work function is different from the second work function.
17. The method of claim 1 wherein the forming an inhibitor further comprises:
selectively forming the inhibitor on the gate dielectric of the second region and not on the gate dielectric of the first region.
18. The method of claim 17 wherein the selectively forming the inhibitor includes forming the inhibitor by stamping.
19. The method of claim 18 wherein the selectively forming the inhibitor includes applying material of the inhibitor by print stamping.
20. The method of claim 19 wherein the applying material of the inhibitor by print stamping includes stamping the wafer with a stamp mask having a layer of inhibitor material at a location on the mask corresponding to the second region.
21. The method of claim 20 wherein the location on the mask is a proud portion of the mask.
22. The method of claim 1 further comprising:
neutralizing the inhibitor after the depositing the first metal layer and prior to the depositing the second metal layer.
23. The method of claim 22 wherein the neutralizing the inhibitor includes removing the inhibitor.
24. The method of claim 22 wherein the neutralizing the inhibitor further includes heating the wafer at 100 C or greater.
25. The method of claim 22 wherein the neutralizing the inhibitor further includes plasma treating the inhibitor.
26. The method of claim 22 wherein the neutralizing the inhibitor further includes plasma etching the inhibitor.
27. The method of claim 22 wherein the neutralizing the inhibitor further includes irradiating the inhibitor with ultra violet (UV) radiation.
28. A method of making a transistor, the method comprising:
selectively forming an inhibitor on a dielectric in a first region of a wafer and not on a dielectric of a second region of the wafer;
selectively depositing a metal layer on the dielectric of the second region, wherein the inhibitor inhibits the deposition of the metal layer on the dielectric of the first region;
forming a gate electrode stack for a transistor in the second region, the gate electrode stack including a structure formed from the metal layer.
29. The method of claim 28 further comprising:
neutralizing the inhibitor after the depositing the metal layer and prior to the forming the gate electrode stack.
30. The method of claim 28 wherein the inhibitor includes a methyl group.
31. The method of claim 28 wherein the inhibitor includes an organosilane.
32. The method of claim 28 wherein the inhibitor is characterized as a self assembling monolayer.
33. The method of claim 28 wherein the selectively farming the inhibitor includes fanning the inhibitor by stamping.
34. The method of claim 28 wherein the selectively fanning the inhibitor includes applying material of the inhibitor by print stamping.
35. The method of claim 28 further comprising:
depositing a second metal layer on a dielectric of the first region;
forming a second gate electrode stack for a second transistor in the first region of the wafer, the second gate electrode stack including a structure formed from the second metal layer.
36. The method of claim 35 further comprising:
neutralizing the inhibitor after the depositing the metal layer and prior to the depositing the second metal layer.
37. A method of making transistors, the method comprising:
selectively forming an inhibitor an a gate dielectric in a first region of a wafer and not on a gate dielectric in a second region of the wafer;
selectively depositing using an atomic layer deposition process, a first metal layer on the gate dielectric of the second region while inhibiting the deposition of the first metal layer on the gate dielectric of the first region;
depositing a second metal layer over the gate dielectric of the first region;
forming a first gate electrode stack for a first transistor in the first region, the first gate electrode stack including a structure fanned from the second metal layer;
forming a second gate electrode stack for a second transistor in the second region, the second gate electrode stack including a structure formed from the first metal layer.
38. The method of claim 37 further comprising:
forming source/drain regions for the first transistor and the second transistor.