Offset compensated sensing for magnetic random access memory
View Patent ↗An offset compensated memory element voltage supply including a differential amplifier with a compensation circuit, and a transistor with a gate connected to the output of the differential amplifier. The compensation circuit of the differential amplifier includes a compensation capacitor that stores a compensation voltage during a calibration phase, and applies the stored compensation voltage to a compensation input of the compensation circuit of the amplifier during a measurement phase. Feedback from a source of the transistor controls the output of the differential amplifier to maintain a standard voltage across a resistive memory element connected to the source during measurement of the resistance of the resistive memory element, and the compensation circuit improves the accuracy of the voltage across the resistive memory element by compensating for an offset voltage of the differential amplifier.
1. A method of sensing a resistance of a resistive memory cell comprising:
holding a column line connected to said memory cell at a predetermined voltage using a first circuit during a sensing operation; and
compensating said first circuit to reduce a voltage offset in said first circuit which would prevent said first circuit from holding said column line at said predetermined voltage.
2. A method as in claim the 1 wherein said first circuit comprises a first differential amplifier circuit.
3. A method as in claim 1 wherein said compensating comprises detecting and storing an offset in said first circuit during a calibration period.
4. A method as in claim 3 wherein said detecting and storing an offset comprises storing a reference value derived from an output of said first circuit.
5. A method as in claim 1 further comprising operatively disconnecting said first circuit from said resistive memory element during a calibration mode period; and
operatively connecting said first circuit to said resistive memory element during a measuring mode period.
6. A method as in claim 1 wherein said holding said column line at a predetermined voltage further comprises comparing a voltage of said column line with a reference voltage, said reference voltage being a voltage substantially equal to said predetermined voltage.
7. A method for sensing a logic value stored by a resistive memory cell, the method comprising:
applying, via a first circuit, a predetermined voltage to a column line coupled to a resistive memory cell to be sensed;
compensating for an offset voltage of said first circuit in order to ensure said predetermined voltage is maintained on said column line;
maintaining a substantially zero difference of potential between said predetermined voltage and a voltage level of a second voltage source coupled to at least one other resistive memory cell that is also coupled to said column line; and
sensing a logic value stored by said resistive memory cell.
8. The method of claim 7 , wherein said act of sensing comprises:
connecting said resistive memory cell between said predetermined voltage and ground.
9. The method of claim 7 , wherein said act of sensing comprises:
sensing a voltage level generated on said column line by a current flow through said resistive memory cell.
10. The method of claim 7 , wherein said act of sensing comprises:
connecting said resistive memory cell between said predetermined voltage and a voltage sufficiently different from said predetermined voltage so as to generate a current flow through said resistive memory cell.