Semiconductor memory cell, array, architecture and device, and method of operating same
View Patent ↗There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory cell and technique of reading data from and writing data into that memory cell. In this regard, in one embodiment of this aspect of the invention, the memory cell includes two transistors which store complementary data states. That is, the two-transistor memory cell includes a first transistor that maintains a complementary state relative to the second transistor. As such, when programmed, one of the transistors of the memory cell stores a logic low (a binary “0”) and the other transistor of the memory cell stores a logic high (a binary “1”). The data state of the two-transistor complementary memory cell may be read and/or determined by sampling, sensing measuring and/or detecting the polarity of the logic states stored in each transistor of complementary memory cell. That is, the two-transistor complementary memory cell is read by sampling, sensing measuring and/or detecting the difference in signals (current or voltage) stored in the two transistors.
1. A semiconductor dynamic random access memory cell for storing a first data state and a second data state, the memory cell comprising:
first and second transistors, wherein each transistor includes:
a source region;
a drain region;
a body region disposed between the source region and the drain region, wherein the body region is electrically floating; and
a gate spaced apart from, and capacitively coupled to, the body region;
wherein each transistor includes (i) a first state representative of a first charge in the body region, and (ii) a second state representative of a second charge in the body region;
wherein the memory cell is in: (1) the first data state when the first transistor is in the first state and the second transistor is in the second state, and (2) the second data state when the first transistor is in the second state and the second transistor is in the first state; and
wherein the memory cell is programmed to a first data state by applying (i) a first control signal to the gate of the first transistor and a second control signal to the drain of the first transistor and (ii) a third control signal to the gate of the second transistor and a fourth control signal to the drain of the second transistor wherein:
the first and third control signals include different voltage amplitudes, and
the second and fourth control signals include substantially the same voltage amplitudes.
2. The semiconductor dynamic random access memory cell of claim 1 wherein the memory cell includes two outputs including a first output connected to the drain region of the first transistor and a second output connected to the drain region of the second transistor.
3. The semiconductor dynamic random access memory cell of claim 2 wherein the gate of the first transistor is connected to the gate of the second transistor.
4. The semiconductor dynamic random access memory cell of claim 3 wherein the source region of the first transistor and the source region of the second transistor are the same region.
5. The semiconductor dynamic random access memory cell of claim 1 wherein the memory cell is programmed to a first data state by applying a fifth control signal to the source of the first transistor and a sixth control signal to the source of the second transistors, and wherein the fifth and sixth control signals include substantially the same voltage amplitudes.
6. The semiconductor dynamic random access memory cell of claim 1 wherein the memory cell includes two outputs including a first output connected to the source region of the first transistor and a second output connected to the source region of the second transistor.
7. The semiconductor dynamic random access memory cell of claim 6 wherein the drain region of the first transistor and the drain region of the second transistor are the same region.
8. A semiconductor memory array, comprising:
a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns, each semiconductor dynamic random access memory cell includes:
first and second transistors, wherein each transistor includes:
a source region;
a drain region;
a body region disposed between the source region and the drain region, wherein the body region is electrically floating: and
a gate spaced apart from, and capacitively coupled to, the body region;
wherein each transistor includes (i) a first state representative of a first charge in the body region, and (ii) a second state representative of a second charge in the body region;
wherein each memory cell is in: (1) the first data state when its first transistor is in the first state and its second transistor is in the second state, and (2) the second data state when its first transistor is in the second state and its second transistor is in the first state; and
wherein each memory cell is programmed to a first data state by applying (i) a first control signal to the gate of the first transistor and a second control signal to the drain of the first transistor and (ii) a third control signal to the gate of the second transistor and a fourth control signal to the drain of the second transistor wherein:
the first and third control signals include different voltage amplitudes, and
the second and fourth control signals include substantially the same voltage amplitudes.
9. The semiconductor memory array of claim 8 further including a comparator having a plurality of inputs to sense the states of the first and second transistors of a semiconductor dynamic random access memory cell of the plurality of semiconductor dynamic random access memory cells, wherein a first input of the comparator is selectively coupled to a first transistor of the semiconductor dynamic random access memory cell and a second input of the comparator is selectively coupled to the second transistor of a semiconductor dynamic random access memory cell.
10. The semiconductor memory array of claim 8 wherein at least one of the rows of semiconductor dynamic random access memory cells includes a source line that is connected to each of the semiconductor dynamic random access memory cells of the row.
11. The semiconductor memory array of claim 8 wherein each row of semiconductor dynamic random access memory cells includes an associated source line which is connected to only the semiconductor dynamic random access memory cells of the associated row.
12. The semiconductor memory array of claim 8 further including:
a comparator having a plurality of inputs to sense the data state of a semiconductor dynamic random access memory cell of the plurality of semiconductor dynamic random access memory cells, wherein a first input of the comparator is selectively coupled to the drain region of the first transistor of the semiconductor dynamic random access memory cell and a second input of the comparator is selectively coupled to the drain of second first transistor of a semiconductor dynamic random access memory cell; and
wherein each row of semiconductor dynamic random access memory cells includes an associated source line which is connected to only the semiconductor dynamic random access memory cells of the row.
13. The semiconductor memory array of claim 8 wherein at least one semiconductor dynamic random access memory cell is programmed in a first data state by performing a clear operation of the first and second transistors of the semiconductor dynamic random access memory cell and then performing a write operation wherein, in response, the first transistor of the semiconductor dynamic random access memory cell is in a first state and the second transistor of the semiconductor dynamic random access memory cell is in a second state.
14. The semiconductor memory array of claim 8 wherein at least one semiconductor dynamic random access memory cell is programmed in a first data state by first placing the first and second transistors of the semiconductor dynamic random access memory cell in a first state and thereafter placing the second transistor of the semiconductor dynamic random access memory cell is in a second state.
15. The semiconductor memory array of claim 14 wherein an unselected portion of the semiconductor memory array is maintained in a fixed state when programming the at least one semiconductor dynamic random access memory cell by applying a write inhibit signal to the transistors of the semiconductor dynamic random access memory cells comprising the unselected portion of the semiconductor memory array.
16. The semiconductor memory array of claim 8 wherein each semiconductor dynamic random access memory cell includes two outputs including a first output connected to the drain region of the first transistor and a second output connected to the drain region of the second transistor.
17. The semiconductor memory array of claim 8 wherein the source region of the first transistor and the source region of the second transistor of each semiconductor dynamic random access memory cell are the same region.
18. The semiconductor memory array of claim 8 wherein the source region of the first transistor and the source region of the second transistor of each semiconductor dynamic random access memory cell are connected to different source lines.
19. The semiconductor memory array of claim 8 wherein each semiconductor dynamic random access memory cell includes two outputs including a first output connected to the source region of the first transistor and a second output connected to the source region of the second transistor.
20. The semiconductor memory array of claim 19 wherein the drain region of the first transistor and the drain region of the second transistor of each semiconductor dynamic random access memory cell are the same region.
21. A semiconductor dynamic random access memory cell for storing a first data state and a second data state, the memory cell comprising:
first and second transistors, wherein each transistor includes:
a source region;
a drain region;
a body region disposed between the source region and the drain region, wherein the body region is electrically floating; and
a gate spaced apart from, and capacitively coupled to, the body region;
wherein each transistor includes (i) a first state representative of a first charge in the body region, and (ii) a second state representative of a second charge in the body region;
wherein the memory cell is in: (1) the first data state when the first transistor is in the first state and the second transistor is in the second state, and (2) the second data state when the first transistor is in the second state and the second transistor is in the first state; and
wherein the memory cell is programmed to a first data state by applying (i) a first control signal to the gate of the first transistor and a second control signal to the drain of the first transistor and (ii) a third control signal to the gate of the second transistor and a fourth control signal to the drain of the second transistor wherein:
the first and third control signals include substantially the same voltage amplitudes, and
the second and fourth control signals include different voltage amplitudes.
22. The semiconductor dynamic random access memory cell of claim 21 wherein the memory cell includes two outputs including a first output connected to the drain region of the first transistor and a second output connected to the drain region of the second transistor.
23. The semiconductor dynamic random access memory cell of claim 22 wherein the gate of the first transistor is connected to the gate of the second transistor.
24. The semiconductor dynamic random access memory cell of claim 23 wherein the source region of the first transistor and the source region of the second transistor are the same region.
25. The semiconductor dynamic random access memory cell of claim 23 wherein the memory cell is programmed to a first data state by applying a fifth control signal to the source of the first transistor and a sixth control signal to the source of the second transistor, and wherein the fifth and sixth control signals include substantially the same voltage amplitudes.
26. The semiconductor dynamic random access memory cell of claim 23 wherein the memory cell includes two outputs including a first output connected to the source region of the first transistor and a second output connected to the source region of the second transistor.
27. The semiconductor dynamic random access memory cell of claim 26 wherein the drain region of the first transistor and the drain region of the second transistor are the same region.
28. A semiconductor memory array, comprising:
a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns, each semiconductor dynamic random access memory cell includes:
first and second transistors, wherein each transistor includes:
a source region;
a drain region;
a body region disposed between the source region and the drain region, wherein the body region is electrically floating; and
a gate spaced apart from, and capacitively coupled to, the body region;
wherein each transistor includes (i) a first state representative of a first charge in the body region, and (ii) a second state representative of a second charge in the body region; and
wherein each memory cell is in: (1) the first data state when its first transistor is in the first state and its second transistor is in the second state, and (2) the second data state when its first transistor is in the second state and its second transistor is in the first state; and
wherein each memory cell is programmed to a first data state by applying (i) a first control signal to the gate of the first transistor and a second control signal to the drain of the first transistor and (ii) a third control signal to the gate of the second transistor and a fourth control signal to the drain of the second transistor wherein:
the first and third control signals include substantially the same voltage amplitudes, and
the second and fourth control signals include different voltage amplitudes.
29. The semiconductor memory array of claim 28 further including a comparator having a plurality of inputs to sense the states of the first and second transistors of a semiconductor dynamic random access memory cell of the plurality of semiconductor dynamic random access, memory cells, wherein a first input of the comparator is selectively coupled to a first transistor of the semiconductor dynamic random access memory cell and a second input of the comparator is selectively coupled to the second transistor of a semiconductor dynamic random access memory cell.
30. The semiconductor memory array of claim 28 wherein at least one of the rows of semiconductor dynamic random access memory cells includes a source line that is connected to each of the semiconductor dynamic random access memory cells of the row.
31. The semiconductor memory array of claim 28 wherein each row of semiconductor dynamic random access memory cells includes an associated source line which is connected to only the semiconductor dynamic random access memory cells of the associated row.
32. The semiconductor memory array of claim 28 further including:
a comparator having a plurality of inputs to sense the data state of a semiconductor dynamic random access memory cell of the plurality of semiconductor dynamic random access memory cells, wherein a first input of the comparator is selectively coupled to the drain region of the first transistor of the semiconductor dynamic random access memory cell and a second input of the comparator is selectively coupled to the drain of second first transistor of a semiconductor dynamic random access memory cell; and
wherein each row of semiconductor dynamic random access memory cells includes an associated source line which is connected to only the semiconductor dynamic random access memory cells of the row.
33. The semiconductor memory array of claim 28 wherein at least one semiconductor dynamic random access memory cell is programmed in a first data state by performing a clear operation of the first and second transistors of the semiconductor dynamic random access memory cell and then performing a write operation wherein, in response, the first transistor of the semiconductor dynamic random access memory cell is in a first state and the second transistor of the semiconductor dynamic random access memory cell is in a second state.
34. The semiconductor memory array of claim 28 wherein at least one semiconductor dynamic random access memory cell is programmed in a first data state by first placing the first and second transistors of the semiconductor dynamic random access memory cell in a first state and thereafter placing the second transistor of the semiconductor dynamic random access memory cell is in a second state.
35. The semiconductor memory array of claim 34 wherein an unselected portion of the semiconductor memory array is maintained in a fixed state when programming the at least one semiconductor dynamic random access memory cell by applying a write inhibit signal to the transistors of the semiconductor dynamic random access memory cells comprising the unselected portion of the semiconductor memory array.
36. The semiconductor memory array of claim 28 wherein each semiconductor dynamic random access memory cell includes two outputs including a first output connected to the drain region of the first transistor and a second output connected to the drain region of the second transistor.
37. The semiconductor memory array of claim 28 wherein gate of the first transistor and the gate of the second transistor of each semiconductor dynamic random access memory cell are each connected to an associated common gate line.
38. The semiconductor memory array of claim 28 wherein the source region of the first transistor and the source region of the second transistor of each semiconductor dynamic random access memory cell are the same region.
39. The semiconductor memory array of claim 28 wherein the source region of the first transistor and the source region of the second transistor of each semiconductor dynamic random access memory cell are connected to different source lines.
40. The semiconductor memory array of claim 28 wherein each semiconductor dynamic random access memory cell includes two outputs including a first output connected to the source region of the first transistor and a second output connected to the source region of the second transistor.
41. The semiconductor memory array of claim 40 wherein the drain region of the first transistor and the drain region of the second transistor of each semiconductor dynamic random access memory cell are the same region.