Patent Assignment
Reel/Frame 025850/0798
Assignment of Assignor's Interest
Recorded: 2011-02-17
Pages: 35
Assignor
INNOVATIVE SILICON ISI S.A.
Executed: 2010-12-09
Assignee
MICRON TECHNOLOGY, INC.
8000 S. FEDERAL WAY, MAIL STOP 525, BOISE, IDAHO, 83716
Covered Properties
(143)
Techniques for Reducing a Voltage Swing
Techniques for Providing a Source Line Plane
Application:
61/153,437 →
Techniques for Simultaneously Driving a Plurality of Source Lines
Techniques for Block Refreshing a Semiconductor Dynamic Random Access Memory Device
Application:
61/111,665 →
Techniques for Forming Contact to Buried Layer in Semiconductor Memory Device
Application:
61/157,504 →
Pseudo Pillar Memory Device and Method for Using Same
Application:
61/165,346 →
Diode as Injector of Holes
Application:
61/173,014 →
Techniques for Reducing Impact of Array Disturbs in a Semiconductor Memory Device
Techniques for Reading from and/or Writing to a Semiconductor Memory Device
Direct Injection Z-Ram Cell Using Soi Finfet
Application:
61/180,810 →
Semiconductor Device
Application:
61/224,741 →
Low Voltage Direct Injection Floating Body Memory Cell
Application:
61/228,934 →
Techniques for Reducing Disturbance in a Semiconductor Device
Current Spike Sense-Amplifier
Application:
61/239,999 →
Techniques for Providing a Direct Injection Semiconductor Memory Device
Techniques for Controlling a Direct Injection Semiconductor Memory Device
Techniques for Providing a Direct Injection Semiconductor Memory Device Having Ganged Carrier Injection Lines
Techniques for Providing a Direct Injection Semiconductor Memory Device
Techniques for Providing a Direct Injection Semiconductor Memory Device
Techniques for Providing a Direct Injection Semiconductor Memory Device
Techniques for Providing a Semiconductor Memory Device
Techniques for Forming a Contact to a Buried Diffusion Layer in a Semiconductor Memory Device
Semiconductor Memory Device
Techniques for Providing a Source Line Plane
Techniques for Providing a Direct Injection Semiconductor Memory Device
Semiconductor Device
Application:
61/314,532 →
Read Circuitry for P-Stripe Z-Ram Low Voltage Architecture
Application:
61/304,067 →
Current Mode Sense Amplifier
Application:
61/310,509 →
Hierarchical Bit Line (Bl) with P-Stripe Architecture
Application:
61/310,573 →
Method and Apparatus for Variable Memory Cell Refresh
Manufacturing process for zero-capacitor random access memory circuits
Application:
60/921,151 →
Manufacturing Process for Zero-Capacitor Random Access Memory Circuits
Semiconductor device with electrically floating body
Application:
60/897,686 →
Semiconductor Device with Electrically Floating Body
Reading technique for memory cell with electrically floating body transistor
Application:
60/932,771 →
Reading Technique for Memory Cell with Electrically Floating Body Transistor
Refreshing Data Of Memory Cells With Electrically Floating Body Transistors
Application:
60/973,139 →
Refreshing Data of Memory Cells with Electrically Floating Body Transistors
Single Transistor Memory Cell
Application:
61/026,705 →
Single Transistor Memory Cell
Vertical Transistor Memory Cell and Array
Application:
61/120,173 →
Vertical Transistor Memory Cell and Array
Recessed Gate Silicon-On-Insulator Floating Body Device With Self-Aligned Lateral Isolation
Application:
61/100,040 →
Recessed Gate Silicon-on-Insulator Floating Body Device with Self-Aligned Lateral Isolation
Semiconductor Device with Floating Gate and Electrically Floating Body
Application:
61/174,075 →
Semiconductor Device with Floating Gate and Electrically Floating Body
Junction-Less P-Stripe Cell
Application:
61/313,986 →
Techniques for Semiconductor Memory Refresh
Application:
61/332,037 →
Techniques for Sensing a Semiconductor Memory Device
Semiconductor Device
Semiconductor Device
Semiconductor Device
Semiconductor Device
Semiconductor Device
Patent:
6,873,539 →
Application:
10/727,742 →
Semiconductor Device
Semiconductor Device
Semiconductor Device
Semiconductor device
Application:
11/904,978 →
Publication:
US US20080165577A1
Semiconductor device
Application:
11/904,977 →
Publication:
US US20080068882A1
Semiconductor Device
Semiconductor Device
Data Storage Device and Refreshing Method for Use with Such Device
Data Storage Device and Refreshing Method for Use with Such Device
Data Storage Device and Refreshing Method for Use with Such Device
Semiconductor Device Utilizing Both Fully and Partially Depleted Devices
Semiconductor Device
Method of operating semiconductor memory device
Application:
60/470,384 →
Dual port one transistor DRAM memory cell and extension to multi-port memory cell
Application:
60/470,318 →
Semiconductor Memory Device and Method of Operating Same
Application:
10/840,009 →
Publication:
US US20040228168A1
Semiconductor Memory Device and Method of Operating Same
Semiconductor Memory Device and Method of Operating Same
Semiconductor Memory Device and Method of Operating Same
Semiconductor Memory Device and Method of Operating Same
Two transistor gain cell
Application:
60/470,385 →
Semiconductor Memory Cell, Array, Architecture and Device, and Method of Operating Same
Offset cancellation technique -- for SOI capacitor-less 1T DRAM
Application:
60/470,462 →
Method and apparatus for generating reference current in semiconductor memory device
Application:
60/470,276 →
Reference Current Generator, and Method of Programming, Adjusting and/or Operating Same
Reference Current Generator, and Method of Programming, Adjusting and/or Operating Same
Integrated circuit device, and method of fabricating same
Application:
60/489,266 →
Integrated Circuit Device, and Method of Fabricating Same
Integrated Circuit Device, and Method of Fabricating Same
Low power programming technique for a one transistor SOI memory device
Application:
60/505,679 →
Low Power Programming Technique for a Floating Body Memory Transistor, Memory Cell, and Memory Array
Low Power Programming Technique for a Floating Body Memory Transistor, Memory Cell, and Memory Array
Programming technique for a memory cell having an electrically floating body transistor
Application:
60/625,248 →
Memory Cell Having an Electrically Floating Body Transistor and Programming Technique Therefor
Method of improving statistical distribution of IC and IC device implementing same
Application:
60/626,745 →
Circuitry for and Method of Improving Statistical Distribution of Integrated Circuits
Sense amplifier circuitry and architecture to write data into and/or read from memory cells
Application:
60/635,709 →
Sense Amplifier Circuitry and Architecture to Write Data into and/or Read from Memory Cells
Sense Amplifier Circuitry and Architecture to Write Data into and/or Read from Memory Cells
Bipolar reading technique for a memory cell having an electrically floating body transistor
Application:
60/638,663 →
Bipolar Reading Technique for a Memory Cell Having an Electrically Floating Body Transistor
Bipolar Reading Technique for a Memory Cell Having an Electrically Floating Body Transistor
Method for reading a memory cell having an electrically floating body transistor, and memory cell, array, and/or device implementing same
Application:
60/703,142 →
Method for reading a memory cell having an electrically floating body transistor, and memory cell and array implementing same
Application:
11/453,594 →
Publication:
US US20070023833A1
Semiconductor memory cell and method of operating same
Application:
60/714,917 →
Semiconductor memory cell and array using bipolar transistor currents to program same
Application:
60/722,139 →
Memory cell, array and device, and method of operating same
Application:
60/728,061 →
Semiconductor memory cell and array using bipolar transistor currents to program and read same
Application:
60/749,385 →
Multilevel memory cell and method for programming and reading same
Application:
60/774,275 →
Memory Cell and Memory Cell Array Having an Electrically Floating Body Transistor, and Methods of Operating Same
Memory Cell and Memory Cell Array Having an Electrically Floating Body Transistor, and Methods of Operating Same
Method and circuitry to generate a reference current for reading a memory cell having an electrically floating body transistor, and device implementing same
Application:
60/718,417 →
Method and Circuitry to Generate a Reference Current for Reading a Memory Cell, and Device Implementing Same
Method and Circuitry to Generate a Reference Current for Reading a Memory Cell, and Device Implementing Same
One transistor memory cell having a mechanically strained electrically floating body region, and method of operating same
Application:
60/728,060 →
One transistor memory cell having strained electrically floating body region, and method of operating same
Application:
11/580,169 →
Publication:
US US20070085140A1
Method and apparatus for varying the programming duration of a floating body transistor, and memory cell, array, and/or device implementing same
Application:
60/731,668 →
Method and apparatus for varying the programming duration of a floating body transistor, and memory cell, array, and/or device implementing same
Application:
60/736,613 →
Method and Apparatus for Varying the Programming Duration and/or Voltage of an Electrically Floating Body Transistor, and Memory Cell Array Implementing Same
Method and Apparatus for Varying the Programming Duration and/or Voltage of an Electrically Floating Body Transistor, and Memory Cell Array Implementing Same
Floating body memory cell and array, and method of operating or controlling same
Application:
60/751,505 →
Electrically Floating Body Memory Cell and Array, and Method of Operating or Controlling Same
Multi-Bit Memory Cell Having Electrically Floating Body Transistor, and Method of Programming and Reading Same
Memory array having a programmable word length, and technique of implementing same
Application:
60/790,111 →
Memory Array Having a Programmable Word Length, and Method of Operating Same
Memory Array Having a Programmable Word Length, and Method of Operating Same
Semiconductor memory array architecture, and method of controlling same
Application:
60/792,820 →
Semiconductor Memory Array Architecture with Grouped Memory Cells, and Method of Controlling Same
Semiconductor memory cell and array using punch-through to program and read same
Application:
60/796,671 →
Semiconductor Memory Cell and Array Using Punch-Through to Program and Read Same
Integrated circuit having memory array including row redundancy, and method of programming, controlling and/or operating same
Application:
60/801,809 →
Integrated Circuit Having Memory Array Including Row Redundancy, and Method of Programming, Controlling and/or Operating Same
Integrated circuit having memory array including ECC and/or column redundancy, and method of programming, controlling and/or operating same
Application:
60/816,416 →
Integrated Circuit Having Memory Array Including Ecc and Column Redundancy and Method of Operating the Same
Integrated circuit having memory array having a segmented bit line architecture and method of controlling and/or operating same
Application:
60/830,084 →
Integrated Circuit Including Memory Array Having a Segmented Bit Line Architecture and Method of Controlling and/or Operating Same
Integrated Circuit Including Memory Array Having a Segmented Bit Line Architecture and Method of Controlling and/or Operating Same
Read Circuitry for an Integrated Circuit Having Memory Cells and/or a Memory Cell Array, and Method of Operating Same
Integrated circuit having voltage generation circuitry for memory cell array, and method of operating and/or controlling same
Application:
60/932,223 →
Integrated Circuit Having Voltage Generation Circuitry for Memory Cell Array, and Method of Operating and /or Controlling Same
Sense amplifier circuitry for integrated circuit having memory cell array, and method of operating same
Application:
60/967,605 →
Sense Amplifier Circuitry for Integrated Circuit Having Memory Cell Array, and Method of Operating Same
Integrated circuit having memory cell array including barriers, and method of manufacturing same
Application:
61/004,672 →
Integrated Circuit Having Memory Cell Array Including Barriers, and Method of Manufacturing Same
Integrated circuit having memory cell array, and method of manufacturing same
Application:
61/007,103 →
Integrated Circuit Having Memory Cell Array, and Method of Manufacturing Same
Intergrated circuit having memory cells including gate material having high work function, and method of manufacturing same
Application:
61/065,025 →
Integrated Circuit Having Memory Cells Including Gate Material Having High Work Function, and Method of Manufacturing Same
Integrated circuit having electrical isolation trenches, mask technology and method of manufacturing same
Application:
61/065,485 →
Integrated Circuit Having Electrical Isolation Regions, Mask Technology and Method of Manufacturing Same
Application:
12/368,333 →
Publication:
US US20090200635A1
Related Assignments
(11)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Nov 24, 2009
From: KWON, JUNGTAE; KIM, DAVID; BHARDWAJ, SUNIL
To: INNOVATIVE SILICON ISI SA
Reel/Frame 023564/0260 →
Assignment of Assignor's Interest
Dec 16, 2009
From: LUTHRA, YOGESH; FISCH, DAVID EDWARD
To: INNOVATIVE SILICON ISI SA
Reel/Frame 023663/0805 →
Assignment of Assignor's Interest
Feb 1, 2010
From: CARMAN, ERIC
To: INNOVATIVE SILICON ISI SA
Reel/Frame 023879/0581 →
Security Interest
May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
Patent Security Agreement
Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
Assignment of Assignor's Interest
Sep 1, 2016
From: MICRON TECHNOLOGY, INC
To: OVONYX MEMORY TECHNOLOGY, LLC
Reel/Frame 039974/0496 →
Corrective Assignment to Correct the Replace Erroneously Filed Patent #7358718 with the Correct Patent #7358178 Previously Recorded on Reel 038669 Frame 0001. Assignor(S) Hereby Confirms the Security Interest.
Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
Security Interest
Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
Release of Security Interest
Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
Release of Security Interest
Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
Release of Security Interest
Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →