Techniques for providing a source line plane
View Patent ↗Techniques for providing a source line plane are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus for providing a source line plane. The apparatus may comprise a source line plane coupled to at least one constant voltage source. The apparatus may also comprise a plurality of memory cells arranged in an array of rows and columns, each memory cell including one or more memory transistors. Each of the one or more memory transistors may comprise a first region coupled to the source line plane, a second region coupled to a bit line, a body region disposed between the first region and the second region, wherein the body region may be electrically floating, and a gate coupled to a word line and spaced apart from, and capacitively coupled to, the body region.
1. An apparatus for providing a source line plane comprising:
a source line plane coupled to at least one constant voltage source, wherein the source line plane is at least one of a source line grid and a single plate; and
a plurality of memory cells arranged in an array of rows and columns, each memory cell including one or more memory transistors comprising:
a first region coupled to the source line plane;
a second region coupled to a bit line;
a body region disposed between the first region and the second region, wherein the body region is electrically floating; and
a gate coupled to a word line and spaced apart from, and capacitively coupled to, the body region.
2. The apparatus according to claim 1 , wherein the at least one constant voltage source provides at least one connection to ground.
3. The apparatus according to claim 2 , wherein the at least one constant voltage source provides at least one internal ground connection associated with the plurality of memory cells.
4. The apparatus according to claim 2 , wherein the at least one constant voltage source provides at least one external ground connection coupled to the plurality of memory cells.
5. The apparatus according to claim 1 , wherein the at least one constant voltage source provides a connection to at least one voltage potential.
6. The apparatus according to claim 5 , wherein the at least one constant voltage source provides at least one internal voltage potential associated with the plurality of memory cells.
7. The apparatus according to claim 5 , wherein the at least one constant voltage source provides at least one external voltage potential coupled to the plurality of memory cells.
8. The apparatus according to claim 1 , wherein the source line plane comprises a plurality of source lines coupled to the plurality of memory cells.
9. The apparatus according to claim 1 , wherein the first region is coupled to the source line plane via a source line.
10. The apparatus according to claim 1 , wherein the plurality of memory cells are arranged in a plurality of sub-arrays of rows and columns.
11. The apparatus according to claim 10 , wherein the source line plane is associated with each of the plurality of sub-arrays of memory cells.
12. The apparatus according to claim 11 , wherein the source line plane is a comprehensive source line plane based at least in part on its association with the each of the plurality of sub-arrays of memory cells.
13. The apparatus according to claim 12 , wherein the comprehensive source line plane is coupled to the at least one constant voltage source.
14. The apparatus according to claim 1 , wherein the source line plane includes a plurality of sub-layers of at least one of a source line grid and a single plate.
15. A method for providing a source line plane comprising the steps of:
coupling a source line plane to at least one constant voltage source, wherein the source line plane is at least one of a source line grid and a single plate; and
arranging a plurality of memory cells in an array of rows and columns, each memory cell including one or more memory transistors comprising:
a first region coupled to the source line plane;
a second region coupled to a bit line;
a body region disposed between the first region and the second region, wherein the body region is electrically floating; and
a gate coupled to a word line and spaced apart from, and capacitively coupled to, the body region.
16. The method according to claim 15 , wherein the at least one constant voltage source provides at least one connection to ground.
17. The method according to claim 15 , wherein the at least one constant voltage source provides a connection to at least one voltage potential.
18. The method according to claim 15 , wherein the source line plane comprises a plurality of source lines coupled to the plurality of memory cells.
19. The method according to claim 15 , wherein the first region is coupled to the source line plane via a source line.
20. The method according to claim 15 , wherein the at least one constant voltage source is at least one internal voltage source associated with the plurality of memory cells.
21. The method according to claim 15 , wherein the at least one constant voltage source is at least one external voltage source coupled to the plurality of memory cells.
22. The method according to claim 15 , wherein the plurality of memory cells are arranged in a plurality of sub-arrays of rows and columns.
23. The method according to claim 22 , wherein the source line plane is associated with each of the plurality of sub-arrays of memory cells.
24. The method according to claim 23 , wherein the source line plane is a comprehensive source line plane based at least in part on its association with the each of the plurality of sub-arrays of memory cells.
25. The method according to claim 24 , wherein the comprehensive source line plane is coupled to the at least one constant voltage source.