Method and apparatus for varying the programming duration and/or voltage of an electrically floating body transistor, and memory cell array implementing same
View Patent ↗There are many inventions described herein as well as many aspects and embodiments of those inventions, for example, circuitry and techniques for reading, writing and/or operating semiconductor memory cells of a memory cell array, including, for example, electrically floating body transistors in which an electrical charge is stored in the body of the transistor. In one aspect, the present inventions are directed to one or more independently controllable parameters of a memory operation (e.g., restore, write, refresh), to program or write a data state into a memory cell. In one embodiment, the parameter is the amount of time of programming or writing a predetermined data state into a memory cell. In another embodiment, the controllable parameter is the amplitude of the voltage of the control signals applied to the gate, drain region and/or source region during programming or writing a predetermined data state into a memory cell. Indeed, the controllable parameters may be both temporal and voltage amplitude. Notably, the memory cell array may comprise a portion of an integrated circuit device, for example, logic device (e.g., a microprocessor) or a portion of a memory device (e.g., a discrete memory).
1. An integrated circuit device comprising:
a memory cell array having a plurality of dynamic random access memory cells, wherein each dynamic random access memory cell stores at least one data state including a first data state or a second data state;
circuitry, coupled to the memory cell array, to program one or more of the memory cells, wherein the circuitry includes:
control signal generation circuitry, coupled to the memory cells, to generate control signals, having temporal characteristics, of a first predetermined program operation and a second predetermined program operation; and
programmable duration circuitry, coupled to the control signal generation circuitry, to control the temporal characteristics of one or more control signals of the first predetermined program operation and the second predetermined program operation; and
wherein the temporal characteristics of the one or more control signals of the first predetermined program operation are different from the temporal characteristics of corresponding control signals of the second predetermined program operation.
2. The integrated circuit device of claim 1 wherein the programmable duration circuitry includes a plurality of circuits including:
a first circuit to control the temporal characteristics of one or more control signals of a write operation; and
a second circuit to control the temporal characteristics of one or more control signals of a refresh operation.
3. The integrated circuit device of claim 1 wherein the programmable duration circuitry includes a plurality of circuits including:
a first circuit to control the temporal characteristics of one or more control signals of a write operation; and
a second circuit to control the temporal characteristics of one or more control signals of a restore operation.
4. The integrated circuit device of claim 1 wherein the programmable duration circuitry includes a plurality of circuits including:
a first circuit to control the temporal characteristics of one or more control signals of a write operation;
a second circuit to control the temporal characteristics of one or more control signals of a refresh operation; and
a third circuit to control the temporal characteristics of one or more control signals of a restore operation.
5. The integrated circuit device of claim 1 wherein the programmable duration circuitry includes a plurality of RC delay circuits.
6. The integrated circuit device of claim 1 wherein the programmable duration circuitry includes:
a first register to store a first value which is representative of a temporal characteristic of one or more control signals of a write operation; and
a second register to store a second value which is representative of a temporal characteristic of one or more control signals of a refresh operation.
7. The integrated circuit device of claim 6 wherein the programmable duration circuitry further includes:
a multiplexer, coupled to the first and second registers, to responsively output one of the first or second values; and
a programmable timer, coupled to the multiplexer, to generate a signal that is representative of the temporal characteristics of one or more control signals of the write operation or the refresh operation using the first value or second value, respectively.
8. The integrated circuit device of claim 1 wherein the programmable duration circuitry includes:
a first register to store a first value which is representative of a temporal characteristic of one or more control signals of a write operation;
a second register to store a second value which is representative of a temporal characteristic of one or more control signals of a refresh operation; and
a third register to store a third value which is representative of a temporal characteristic of one or more control signals of a restore operation.
9. The integrated circuit device of claim 8 wherein the programmable duration circuitry further includes:
a multiplexer, coupled to the first, second and third registers, to responsively output one of the first, second or third values; and
a programmable timer, coupled to the multiplexer, to generate a signal that is representative of the temporal characteristics of one or more control signals of the write operation, the refresh operation or the restore operation using the first value, second value or third value, respectively.
10. The integrated circuit device of claim 1 wherein the circuitry, coupled to the memory cell array, to program one or more of the memory cells for a plurality of predetermined memory operations, further includes:
programmable voltage circuitry, coupled to the control signal generation circuitry, to control the voltage amplitude characteristics of one or more control signals of the first predetermined program operation and the second predetermined program operation; and
wherein the voltage amplitude characteristics of the one or more control signals of the first predetermined program operation are different from the voltage amplitude characteristics of corresponding control signals of the second predetermined program operation.
11. The integrated circuit device of claim 10 wherein the programmable voltage circuitry includes a plurality of circuits including:
a first circuit to control the voltage amplitude characteristics of one or more control signals of a write operation; and
a second circuit to control the voltage amplitude characteristics of one or more control signals of a refresh operation.
12. The integrated circuit device of claim 10 wherein the programmable voltage circuitry includes a plurality of circuits including:
a first circuit to control the voltage amplitude characteristics of one or more control signals of a write operation; and
a second circuit to control the voltage amplitude characteristics of one or more control signals of a restore operation.
13. The integrated circuit device of claim 10 wherein the programmable voltage circuitry includes a plurality of circuits including:
a first circuit to control the voltage amplitude characteristics of one or more control signals of a write operation;
a second circuit to control the voltage amplitude characteristics of one or more control signals of a refresh operation; and
a third circuit to control the voltage amplitude characteristics of one or more control signals of a restore operation.
14. An integrated circuit device comprising:
a memory cell array having a plurality of memory cells, wherein each dynamic random access memory cell stores at least one data state including a first data state or a second data state;
circuitry, coupled to the memory cell array, to program one or more of the memory cells, wherein the circuitry includes:
control signal generation circuitry, coupled to the memory cells, to generate control signals, having voltage amplitude characteristics, of a first predetermined program operation and a second predetermined program operation; and
programmable voltage circuitry, coupled to the control signal generation circuitry, to control the voltage amplitude characteristics of one or more control signals of the first predetermined program operation and the second predetermined program operation; and
wherein the voltage amplitude characteristics of the one or more control signals of the first predetermined program operation are different from the voltage amplitude characteristics of corresponding control signals of the second predetermined program operation.
15. The integrated circuit device of claim 14 wherein the programmable voltage circuitry includes a plurality of circuits including:
a first circuit to control the voltage amplitude characteristics of one or more control signals of a write operation; and
a second circuit to control the voltage amplitude characteristics of one or more control signals of a refresh operation.
16. The integrated circuit device of claim 14 wherein the programmable voltage circuitry includes a plurality of circuits including:
a first circuit to control the voltage amplitude characteristics of one or more control signals of a write operation; and
a second circuit to control the voltage amplitude characteristics of one or more control signals of a restore operation.
17. The integrated circuit device of claim 14 wherein the programmable voltage circuitry includes a plurality of circuits including:
a first circuit to control the voltage amplitude characteristics of one or more control signals of a write operation;
a second circuit to control the voltage amplitude characteristics of one or more control signals of a refresh operation; and
a third circuit to control the voltage amplitude characteristics of one or more control signals of a restore operation.
18. The integrated circuit device of claim 14 wherein the programmable voltage circuitry includes:
a first register to store a first value which is representative of a voltage amplitude characteristic of one or more control signals of a write operation; and
a second register to store a second value which is representative of a voltage amplitude characteristic of one or more control signals of a refresh operation.
19. The integrated circuit device of claim 14 wherein the programmable duration circuitry includes:
a first register to store a first value which is representative of a voltage amplitude characteristic of one or more control signals of a write operation;
a second register to store a second value which is representative of a voltage amplitude characteristic of one or more control signals of a refresh operation; and
a third register to store a third value which is representative of a voltage amplitude characteristic of one or more control signals of a restore operation.
20. The integrated circuit device of claim 14 wherein:
the circuitry to program one or more of the memory cells is means for programming one or more of the memory cells, and wherein:
the control signal generation circuitry is means for generating control signals, having voltage amplitude characteristics, of a first predetermined program operation and a second predetermined program operation, and
the programmable voltage circuitry is means for controlling the voltage amplitude characteristics of one or more control signals of the first predetermined program operation and the second predetermined program operation.
21. The integrated circuit device of claim 1 wherein:
the circuitry to program one or more of the memory cells is means for programming one or more of the memory cells, and wherein:
the control signal generation circuitry is means for generating control signals, having temporal characteristics, of a first predetermined program operation and a second predetermined program operation, and
the programmable duration circuitry is means for controlling the temporal characteristics of one or more control signals of the first predetermined program operation and the second predetermined program operation.