Techniques for sensing a semiconductor memory device
View Patent ↗Techniques for sensing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a memory cell array comprising a plurality of memory cells. The apparatus may also include a first data sense amplifier circuitry including an amplifier transistor having a first region coupled to at least one of the plurality of memory cells via a bit line. The apparatus may further include a data sense amplifier latch circuitry including a first input node coupled to the data sense amplifier circuitry via a second region of the amplifier transistor.
1. An apparatus comprising:
a memory cell array comprising a plurality of memory cells;
first data sense amplifier circuitry comprising an amplifier transistor having a first region coupled to at least one of the plurality of memory cells via a bit line; and
data sense amplifier latch circuitry comprising a first input node coupled to the first data sense amplifier circuitry via a second region of the amplifier transistor; wherein the data sense amplifier latch circuitry stores a data state determined by the first data sense amplifier circuitry.
2. The apparatus according to claim 1 , further comprising a first power source coupled to the first region of the amplifier transistor.
3. The apparatus according to claim 1 , further comprising a second power source coupled to the second region of the amplifier transistor.
4. The apparatus according to claim 1 , further comprising a switch transistor coupled to the first region of amplifier transistor and the second region of the amplifier transistor.
5. The apparatus according to claim 4 , wherein the switch transistor comprises a first region coupled to a first power source and a second region coupled to a second power source.
6. The apparatus according to claim 1 , wherein the data sense amplifier latch circuitry comprises a second input node coupled to second data sense amplifier circuitry.
7. The apparatus according to claim 6 , wherein the data sense amplifier latch circuitry further comprises a plurality of transistors arranged in a cross-coupled configuration that are configured to amplify a voltage or current difference between the first input node and the second input node.
8. The apparatus according to claim 6 , wherein the second data sense amplifier circuitry provides a reference voltage potential to the second input node of the data sense amplifier latch circuitry.
9. The apparatus according to claim 1 , wherein the data sense amplifier latch circuitry comprises a first latch access transistor at the first input node and a second latch access transistor at the second input node.
10. The apparatus according to claim 9 , wherein the data sense amplifier latch circuitry comprises an equalization transistor arranged in series with the first latch access transistor and the second latch access transistor.
11. The apparatus according to claim 1 , further comprising pre-charge circuitry coupled to the bit line.
12. The apparatus according to claim 11 , wherein the pre-charge circuitry comprises a first pre-charge transistor coupled to a control line.
13. The apparatus according to claim 12 , wherein the pre-charge circuitry further comprises a second pre-charge transistor having a first region coupled to the bit line.
14. The apparatus according to claim 13 , wherein the second pre-charge transistor comprises a second region coupled to the first pre-charge transistor.
15. The apparatus according to claim 14 , wherein the second pre-charge transistor further comprises a third region coupled to the second region of the amplifier transistor.
16. The apparatus according to claim 1 , further comprising input/output circuitry coupled to the data sense amplifier latch circuitry.
17. The apparatus according to claim 16 , wherein the input/output circuitry comprises a first input/output transistor coupled to the first input node of the data sense amplifier latch circuitry.
18. The apparatus according to claim 17 , wherein the input/output circuitry further comprises a second input/output transistor coupled to a second input node of the data sense amplifier latch circuitry.
19. The apparatus according to claim 1 , wherein the data sense amplifier latch circuitry comprises a second input node coupled to the bit line.
20. The apparatus according to claim 19 , wherein a voltage potential at the first input node of the data sense amplifier latch circuitry is inversely related to a voltage potential at the second input node of the data sense amplifier latch circuitry.