Integrated circuit having memory cell array, and method of manufacturing same
View Patent ↗An integrated circuit device (e.g., a logic device or a memory device) having (i) a memory cell array which includes a plurality of memory cells (for example, memory cells having electrically floating body transistors) arranged in a matrix of rows and columns, wherein each memory cell includes at least one transistor having a gate, gate dielectric and first, second and body regions, wherein: (i) the gate and gate dielectric are disposed on or above the first semiconductor layer that is disposed on or above an insulating layer or region, (ii) the body region of each transistor is electrically floating, (iii) the transistors of adjacent memory cells include a layout that provides a common first region, and (iv) the first regions of the transistors are comprised of a semiconductor material which is different from the material of the first semiconductor layer. Also disclosed are inventive methods of manufacturing, for example, such integrated circuit devices.
1. A method of manufacture of an integrated circuit device having a memory cell array including a plurality of memory cells, arranged in a matrix of rows and columns, wherein each memory cell includes at least one transistor having a gate, a gate dielectric, and first, second, and body regions, the method comprising:
forming the gate and gate dielectric on or over a first semiconductor layer that is disposed on or over an insulating layer or region;
forming a cap structure on top and side surfaces of the gate, the gate dielectric, and at least a portion of the first semiconductor layer, wherein the cap structure has a first lateral boundary;
removing a portion of the first semiconductor layer between transistors of adjacent memory cells coinciding with at least a portion of the first lateral boundary of the cap structure such that at least one remaining portion of the first semiconductor layer has a second lateral boundary that extends beyond at least one lateral boundary of the gate and gate dielectric and coincides with at least a portion of the first lateral boundary of the cap structure, wherein the body region is formed in the at least one remaining portion of the first semiconductor layer;
forming at least a portion of the first region by disposing a semiconductor material on the insulating layer or region where the portion of the first semiconductor layer was removed, wherein the semiconductor material extends continuously between transistors of adjacent memory cells such that first regions of transistors of adjacent memory cells form a common first region, and wherein the semiconductor material is a different type and/or crystalline structure relative to a type and/or crystalline structure of material comprising the first semiconductor layer;
forming at least a portion of the second region; and
forming an electrical contact on an associated common first region.
2. The method of manufacture of claim 1 wherein forming at least a portion of the second region further includes disposing the semiconductor material on the insulating layer or region where another portion of the first semiconductor layer was removed between transistors of adjacent memory cells.
3. The method of manufacture of claim 2 wherein second regions of transistors of adjacent memory cells form a common second region.
4. The method of manufacture of claim 2 wherein the second region of each transistor further includes a portion of the first semiconductor layer which is disposed adjacent to the associated body region of the transistor.
5. The method of manufacture of claim 1 wherein the semiconductor material of the first regions include a material having a crystalline structure that is different from the crystalline structure of the material of the first semiconductor layer.
6. The method of manufacture of claim 1 wherein the first region of each transistor further includes a portion of the first semiconductor layer which is disposed adjacent to the associated body region of the transistor.
7. The method of manufacture of claim 1 wherein the semiconductor material of the first regions includes doped polycrystalline silicon and the first semiconductor layer is monocrystalline silicon.
8. The method of manufacture of claim 1 wherein the first regions are comprised of a plurality of semiconductor materials.
9. The method of manufacture of claim 1 wherein removing a portion of the first semiconductor layer between transistors of adjacent memory cells includes removing the portion of the first semiconductor layer to expose the insulating layer or region.
10. The method of manufacture of claim 1 wherein the first semiconductor layer is silicon and the semiconductor material of the first regions includes at least one of silicon-germanium, gallium arsenide, silicon carbide, polycrystalline silicon, and amorphous silicon.
11. The method of manufacture of claim 1 wherein forming the gate and gate dielectric on or over a first semiconductor layer includes forming the gate and gate dielectric above the first semiconductor layer that is disposed on or over the insulating layer or region.
12. The method of manufacture of claim 1 wherein forming the gate and gate dielectric on or over a first semiconductor layer that is disposed on or over the insulating layer or region includes forming the gate and gate dielectric on or over the first semiconductor layer that is disposed above the insulating layer or region.
13. The method of manufacture of claim 1 wherein forming the gate and gate dielectric on or over a first semiconductor layer that is disposed on or over the insulating layer or region includes forming the gate and gate dielectric above the first semiconductor layer that is disposed above the insulating layer or region.