Techniques for providing a direct injection semiconductor memory device
View Patent ↗Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. At least one of the plurality of memory cells may include a first region coupled to a respective bit line of the array and a second region coupled to a respective source line of the array. At least one of the plurality of memory cells may also include a body region spaced apart from and capacitively coupled to a respective word line of the array, wherein the body region may be electrically floating and disposed between the first region and the second region. At least one of the plurality of memory cells may further include a third region coupled to a respective carrier injection line of the array and wherein the respective carrier injection line may be one of a plurality of carrier injection lines in the array that are coupled to each other.
1. A direct injection semiconductor memory device comprising:
a plurality of memory cells arranged in an array of rows and columns, at least one of the plurality of memory cells comprising:
a first region coupled to a respective bit line of the array;
a second region coupled to a respective source line of the array;
a body region spaced apart from and capacitively coupled to a respective word line of the array, wherein the body region is electrically floating and disposed between the first region and the second region; and
a third region coupled to a respective carrier injection line of the array;
wherein the respective carrier injection line is one of a plurality of carrier injection lines in the array that are coupled to each other.
2. The direct injection semiconductor memory device according to claim 1 , wherein the first region, the body region, and the second region form a first bipolar transistor.
3. The direct injection semiconductor memory device according to claim 2 , wherein the body region, the second region, and the third region form a second bipolar transistor.
4. The direct injection semiconductor memory device according to claim 1 , wherein the respective carrier injection line contacts the third region.
5. The direct injection semiconductor memory device according to claim 1 , further comprising a constant voltage source applying a positive bias to the third region via the respective carrier injection line.
6. The direct injection semiconductor memory device according to claim 1 , wherein the respective bit line extends from the first region perpendicular to at least a portion of at least one of the respective source line, the respective word line, and the respective carrier injection line.
7. The direct injection semiconductor memory device according to claim 1 , wherein the respective word line extends from near the body region horizontally parallel to at least a portion of at least one of the respective source line and the respective carrier injection line.
8. The direct injection semiconductor memory device according to claim 1 , wherein the respective source line extends from the second region horizontally parallel to at least one of the respective word line and the respective carrier injection line.
9. The direct injection semiconductor memory device according to claim 1 , further comprising a fourth region disposed between the third region and a substrate.
10. The direct injection semiconductor memory device according to claim 9 , wherein the fourth region is N-doped region and the substrate is a P-type substrate.
11. The direct injection semiconductor memory device according to claim 1 , wherein the first region and the second region are N-doped regions.
12. The direct injection semiconductor memory device according to claim 1 , wherein the body region and the third region are P-doped regions.
13. A method for biasing a direct injection semiconductor memory device comprising the steps of:
applying a plurality of voltage potentials to a least one of a plurality of memory cells arranged in an array of rows and columns, wherein applying a plurality of voltage potentials to the at least one of a plurality of memory cells comprises:
applying a first voltage potential to a first region via a respective bit line of the array;
applying a second voltage potential to a second region via a respective source line of the array;
applying a third voltage potential to a respective word line of the array, wherein the word line is spaced apart from and capacitively to a body region that is electrically floating and disposed between the first region and the second region; and
applying a fourth voltage potential to a third region via a respective carrier injection line of the array; and
wherein the respective carrier injection lines is one of a plurality of the carrier injection lines in the array that are coupled to each other.
14. The method according to claim 13 , further comprising increasing the third voltage potential applied to the respective word line from the third voltage potential applied to the respective word line during a hold operation to perform a read operation.
15. The method according to claim 13 , further comprising increasing the second voltage potential applied to the respective source line from the second voltage potential applied to the respective source line during a hold operation to perform a read operation.
16. The method according to claim 13 , further comprising increasing the first voltage potential applied to the respective bit line from the first voltage potential applied to the respective bit line during a hold operation in order to reduce a disturbance during a read operation.
17. The method according to claim 13 , further comprising maintaining the third voltage potential applied to the respective word line from the third voltage potential applied to the respective word line during a hold operation to perform a write logic high operation.
18. The method according to claim 13 , further comprising lowering the second voltage potential applied to the second region via the respective source line from the second voltage potential applied to the second region during a hold operation to perform a write logic high operation.
19. The method according to claim 13 , further comprising increasing the third voltage potential applied to the respective word line from the third voltage potential applied to the respective word line during a hold operation to perform a write logic low operation.
20. The method according to claim 13 , further comprising increasing the second voltage potential applied to the respective source line from the second voltage potential applied to the respective source line during a hold operation to perform a write logic low operation.
21. The method according to claim 13 , further comprising maintaining the first voltage potential applied to the respective bit line from the first voltage potential applied to the respective bit line during a hold operation to perform a write logic low operation.
22. The method according to claim 13 , further comprising increasing the first voltage potential applied to the respective bit line during a write logic low operation from the first voltage potential applied to the respective bit line during a hold operation to maintain a logic high stored in the memory cell.