Techniques for providing a direct injection semiconductor memory device having ganged carrier injection lines
View Patent ↗Techniques for providing a direct injection semiconductor memory device having ganged carrier injection lines are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a first region coupled to a bit line and a second region coupled to a source line. The apparatus may also comprise a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The apparatus may further comprise a third region coupled to a constant voltage source via a carrier injection line configured to inject charges into the body region through the second region.
1. A direct injection semiconductor memory device comprising:
a first region coupled to a bit line;
a second region coupled to a source line;
a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region; and
a third region coupled to a constant voltage source via a carrier injection line configured to inject charges into the body region through the second region;
wherein the third region, the second region, the body region, and the first region are disposed in a sequential contiguous configuration extending substantially vertically from a horizontal plane defined by at least a substrate.
2. The direct injection semiconductor memory device according to claim 1 , wherein the first region, the body region, and the second region forms a first bipolar transistor.
3. The direct injection semiconductor memory device according to claim 2 , wherein the body region, the second region, and the third region forms a second bipolar transistor.
4. The direct injection semiconductor memory device according to claim 1 , wherein the carrier injection line contacts the third region.
5. The direct injection semiconductor memory device according to claim 1 , wherein the constant voltage source applies a positive bias to the third region via the carrier injection line.
6. The direct injection semiconductor memory device according to claim 1 , wherein the constant voltage source applies 0V or a negative bias to the third region via the carrier injection line.
7. The direct injection semiconductor memory device according to claim 1 , wherein the constant voltage source is coupled to a plurality of the carrier injection lines.
8. The direct injection semiconductor memory device according to claim 1 , wherein the bit line extends from the first region perpendicular to at least one of the source line, the word line, and the carrier injection line.
9. The direct injection semiconductor memory device according to claim 1 , wherein the word line extends from near the body region horizontally parallel to the carrier injection line.
10. The direct injection semiconductor memory device according to claim 1 , wherein the source line extends from the second region horizontally parallel to at least one of the word line and the carrier injection line.
11. The direct injection semiconductor memory device according to claim 1 , further comprising a fourth region disposed between the third region and the substrate.
12. The direct injection semiconductor memory device according to claim 11 , wherein the fourth region is N-doped region and the substrate is a P-type substrate.
13. The direct injection semiconductor memory device according to claim 1 , wherein the first region and the second region are N-doped regions.
14. The direct injection semiconductor memory device according to claim 1 , wherein the body region and the third region are P-doped regions.
15. A method for providing a direct injection semiconductor memory device comprising the steps of:
coupling a first region to a bit line;
coupling a second region to a source line;
coupling a body region spaced apart from and capacitively to a word line, wherein the body region is electrically floating and disposed between the first region and the second region; and
coupling a third region to a constant voltage source via a carrier injection line configured to inject charges into the body region through the second region;
wherein the third region, the second region, the body region, and the first region are disposed in a sequential contiguous configuration extending substantially vertically from a horizontal plane defined by at least a substrate.
16. The method according to claim 15 , wherein the constant voltage source applies a positive bias to the third region via the carrier injection line.
17. The method according to claim 15 , wherein the constant voltage source applies 0V or a negative bias to the third region via the carrier injection line.
18. The method according to claim 15 , wherein the constant voltage source is coupled to a plurality of the carrier injection lines.
19. The method according to claim 15 , wherein the bit line extends from the first region perpendicular to at least one of the source line, the word line, and the carrier injection line.
20. The method according to claim 15 , wherein the word line extends from near the body region horizontally parallel to the carrier injection line.
21. The method according to claim 15 , wherein the source line extends from the second region horizontally parallel to at least one of the word line and the carrier injection line.
22. The method according to claim 15 , further comprising a fourth region disposed between the third region and the substrate.
23. The method according to claim 22 , wherein the fourth region is N-doped region and the substrate is a P-type substrate.
24. The method according to claim 15 , wherein the first region and the second region are N-doped regions.
25. The method according to claim 15 , wherein the body region and the third region are P-doped regions.
26. A direct injection semiconductor memory device comprising:
a first region coupled to a bit line;
a second region directly coupled to a source line and capacitively coupled to a first word line;
a body region spaced apart from and capacitively coupled to a second word line, wherein the body region is electrically floating and disposed between the first region and the second region; and
a third region coupled to a carrier injection line;
wherein the first word line provides control signals to a field-effect transistor comprising the third region, the second region, and the body region, and wherein the second word line provides control signals to a bipolar transistor comprising the second region, the body region, and the first region.
27. A direct injection semiconductor memory device comprising:
a first region coupled to a bit line;
a second region coupled to a source line;
a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and substantially disposed between the first region and the second region; and
a third region coupled to a carrier injection line, wherein a first portion of the third region is directly coupled to the second region and a second portion of the third region is directly coupled to the body region.