Semiconductor memory device and method of operating same
View Patent ↗There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this aspect of the invention, the memory device and technique for operating that device that minimizes, reduces and/or eliminates the debilitating affects of the charge pumping phenomenon. This embodiment of the present invention employs control signals that minimize, reduce and/or eliminate transitions of the amplitudes and/or polarities. In another embodiment, the present invention is a semiconductor memory device including a memory array comprising a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns. Each semiconductor dynamic random access memory cell includes a transistor having a source region, a drain region, a electrically floating body region disposed between and adjacent to the source region and the drain region, and a gate spaced apart from, and capacitively coupled to, the body region. Each transistor includes a first state representative of a first charge in the body region, and a second data state representative of a second charge in the body region. Further, each row of semiconductor dynamic random access memory cells includes an associated source line which is connected to only the semiconductor dynamic random access memory cells of the associated row.
1. A semiconductor memory array, comprising:
a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns, each semiconductor dynamic random access memory cell includes at least one transistor having:
a source region;
a drain region;
a body region disposed between the source region and the drain region,
wherein the body region is electrically floating; and
a gate spaced apart from, and capacitively coupled to, the body region;
wherein each memory cell includes (1) a first data state which corresponds to a first charge in the body region of the transistor of the memory cell, and (2) a second data state which corresponds to a second charge in the body region of the transistor of the memory cell; and
wherein the source region of the transistor of each memory cell corresponding to a first row of semiconductor dynamic random access memory cells and a second row of semiconductor dynamic random access memory cells is connected to a first source line, and wherein the first and second rows of memory cells are adjacent rows and the gate of the transistor of each memory cell corresponding to the first row of semiconductor dynamic random access memory cells is connected to a first word line and the gate of the transistor of each memory cell corresponding to the second row of semiconductor dynamic random access memory cells is connected to a second word line; and
wherein one or more predetermined memory cells of the first row are programmed to the second data state by programming each memory cell of the first row to the first data state and thereafter programming the one or more predetermined memory cells of the first row to the second data state.
2. The semiconductor memory array of claim 1 wherein the transistor of each memory cell of the first row of semiconductor dynamic random access memory cells shares a source region with a transistor of an adjacent memory cell of a second row of semiconductor dynamic random access memory cells.
3. The semiconductor memory array of claim 2 wherein the drain region of the transistor of each memory cell of the first row of semiconductor dynamic random access memory cells is connected to a bit line that is different from the bit line of the adjacent memory cell of the second row of semiconductor dynamic random access memory cells.
4. The semiconductor memory array of claim 2 wherein each memory cell of the first row is programmed to the first data state by applying a control signal, having a first amplitude, to the gate of the transistor of each memory cell of the first row, a control signal, having a second amplitude, to the drain region of the transistor of each memory cell of the first row and a control signal, having a third amplitude, to the source region of the transistor of each memory cell of the first row.
5. The semiconductor memory array of claim 4 wherein the one or more predetermined memory cells of the first row are programmed to the second data state by applying (1) a control signal, having a fourth amplitude, to the gate of the transistor of each memory cell of the one or more predetermined memory cells, (2) a control signal, having an fifth amplitude, to the drain region of the transistor of each memory cell of the one or more predetermined memory cells, and (3) a control signal, having a sixth amplitude, to the source region of the transistor of each memory cell of the one or more predetermined memory cells of the first row.
6. The semiconductor memory array of claim 5 wherein an unselected memory cell of the first row is maintained in the first data state, while the one or more predetermined memory cells are programmed to the second data state.
7. The semiconductor memory array of claim 1 wherein the first word line and the second word line are connected.
8. The semiconductor memory array of claim 1 wherein memory cells of the first row of semiconductor dynamic random access memory cells and the second row of semiconductor dynamic random access memory cells are read from or written to simultaneously.
9. A semiconductor memory array, comprising:
a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns, each semiconductor dynamic random access memory cell includes at least one transistor having:
a source region;
a drain region;
a body region disposed between the source region and the drain region,
wherein the body region is electrically floating; and
a gate spaced apart from, and capacitively coupled to, the body region;
wherein each transistor includes a first state representative of a first charge in the body region, and a second data state representative of a second charge in the body region; and
wherein:
the source region of the transistor of each memory cell corresponding to a first row of semiconductor dynamic random access memory cells is connected to a first source line;
the gate of the transistor of each memory cell corresponding to the first row of semiconductor dynamic random access memory cells is connected to a first word line;
the drain region of the transistor of each memory cell of the first row of semiconductor dynamic random access memory cells is connected to a different bit line; and
the source region of the transistor of each memory cell corresponding to a second row of semiconductor dynamic random access memory cells is connected to the first source line;
the gate of the transistor of each memory cell corresponding to the second row of semiconductor dynamic random access memory cells is connected to a second word line;
the drain region of the transistor of each memory cell of the second row of semiconductor dynamic random access memory cells is connected to a different bit line; and
wherein the first and second rows of semiconductor dynamic random access memory cells are adjacent rows; and
wherein one or more predetermined memory cells of the first row are programmed to the second data state by programming each memory cell of the first row to the first data state and thereafter programming the one or more predetermined memory cells of the first row to the second data state.
10. The semiconductor memory array of claim 9 wherein the transistor of each memory cell of the first row of semiconductor dynamic random access memory cells shares a source region with a transistor of an adjacent memory cell of a second row of semiconductor dynamic random access memory cell.
11. The semiconductor memory array of claim 10 wherein the drain region of the transistor of each memory cell of the first row of semiconductor dynamic random access memory cells is connected to a bit line that is different from the bit line of the adjacent memory cell of the second row of semiconductor dynamic random access memory cells.
12. The semiconductor memory array of claim 11 wherein each memory cell of the first row is programmed to a the first data state by applying control signal, having a first amplitude, to the gate of the transistor of each memory cell of the first row of semiconductor dynamic random access memory cells, a control signal, having a second amplitude, to the drain region of the transistor of each memory cell of the first row of semiconductor dynamic random access memory cells, and a control signal having a third amplitude, to the source region of the transistor of each memory cell of the first row of semiconductor dynamic random access memory cells.
13. The semiconductor memory array of claim 12 wherein the one or more predetermined memory cells of the first row of semiconductor dynamic random access memory cells are programmed to the second data state by applying a control signal, having the fourth amplitude, to the gate of the transistor of each memory cell of the one or more predetermined memory cells, a control signal, having a fifth amplitude, to the drain region of the transistor of each memory cell of the one or more predetermined memory cells, and a control signal, having a sixth amplitude, to the source region of the transistor of each memory cell of the one or more predetermined memory cells.
14. The semiconductor memory array of claim 13 wherein an unselected memory cell of the first row of semiconductor dynamic random access memory cells is maintained in the first data state, while each memory cell of the predetermined memory cells are programmed to the second data state, by applying a control signal, having the fourth amplitude, to the gate of the transistor of the unselected memory cell and a control signal, having an seventh amplitude, to the drain region of the transistor of the unselected memory cell.
15. The semiconductor memory array of claim 9 wherein all of the memory cells of the second row are maintained in an inhibit state while the memory cells of the first row are read.
16. The semiconductor memory array of claim 9 wherein the transistor of each memory cell of the first row of semiconductor dynamic random access memory cells shares a drain region with the transistor of an adjacent memory cell of the second row of semiconductor dynamic random access memory cells.
17. The semiconductor memory array of claim 9 wherein the first word line and the second word line are connected.
18. The semiconductor memory array of claim 9 wherein memory cells of the first row of semiconductor dynamic random access memory cells and the second row of semiconductor dynamic random access memory cells are read from or written to simultaneously.
19. A semiconductor memory array, disposed in or on a semiconductor region or layer which resides on or above an insulating region or layer of a substrate, the semiconductor memory array, comprising:
a plurality of semiconductor dynamic random access memory cells disposed in or on the semiconductor region or layer and arranged in a matrix of rows and columns, each semiconductor dynamic random access memory cell includes at least one transistor having:
a source region;
a drain region;
a body region disposed between the source region, the drain region and the insulating region or layer of the substrate, wherein the body region is electrically floating; and
a gate spaced apart from, and capacitively coupled to, the body region;
wherein each memory cell includes (1) a first data state which corresponds to a first charge in the body region of the transistor of the memory cell, and (2) a second data state which corresponds to a second charge in the body region of the transistor of the memory cell; and
wherein the source region of the transistor of each memory cell corresponding to a first row of semiconductor dynamic random access memory cells and a second row of semiconductor dynamic random access memory cells is connected to a first source line, and wherein the first and second rows of memory cells are adjacent rows and the gate of the transistor of each memory cell corresponding to the first row of semiconductor dynamic random access memory cells is connected to a first word line and the gate of the transistor of each memory cell corresponding to the second row of semiconductor dynamic random access memory cells is connected to a second word line; and
wherein one or more predetermined memory cells of the first row are programmed to the second data state by programming each memory cell of the first row to the first data state and thereafter programming the one or more predetermined memory cells of the first row to the second data state.
20. The semiconductor memory array of claim 19 wherein the transistor of each memory cell of the first row of semiconductor dynamic random access memory cells shares a source region with a transistor of an adjacent memory cell of a second row of semiconductor dynamic random access memory cells, wherein the first and second rows of memory cells are adjacent rows.
21. The semiconductor memory array of claim 20 wherein the drain region of the transistor of each memory cell of the first row of semiconductor dynamic random access memory cells is connected to a bit line that is different from the bit line of the adjacent memory cell of the second row of semiconductor dynamic random access memory cells.
22. The semiconductor memory array of claim 19 wherein the transistor of each memory cell of the first row of semiconductor dynamic random access memory cells shares a drain region with the transistor of an adjacent memory cell of the second row of semiconductor dynamic random access memory cells.
23. The semiconductor memory array of claim 19 wherein the first word line and the second word line are connected.