Method and circuitry to generate a reference current for reading a memory cell, and device implementing same
View Patent ↗There are many inventions disclosed herein. In one aspect, the present inventions are directed to methods and circuitry to control, adjust, determine and/or modify the absolute and/or relative positioning or location (i.e., absolute or relative amount) of reference current which is employed by read circuitry to read the data state of a memory cell during a read operation of one or more memory cells. The control, adjustment, determination and/or modification of the reference current levels may be implemented using many different, distinct and/or diverse techniques and circuitry, including both analog and digital techniques and circuitry.
1. A method of controlling a reference current generation circuit that generates a predetermined reference current which is used by read circuitry during a read operation to data a data state of one or more memory cells, wherein the reference current generation circuit includes (i) a plurality of reference cell circuits including a first reference cell circuit and a second reference cell circuit, each reference cell circuit including a plurality of reference cells, and (ii) a reference current driver, the method comprising:
programming at least one of the reference cells of the first reference cell circuit to one of a plurality of predetermined states;
programming at least one of the reference cells of the second reference cell circuit to one of a plurality of predetermined states, wherein a majority of the reference cells of the reference cell circuits is programmed to a second state and a minority of the reference cells of the reference cell circuits is programmed to a first state; and
outputting the predetermined reference current, wherein the amount of the predetermined reference current is associated with the programmed states of the reference cells of the plurality of reference cell circuits.
2. The method of claim 1 wherein programming the at least one of the reference cells of the first reference cell circuit to one of a plurality of predetermined states includes storing a first charge in a body region of a transistor of the at least one reference cell of the first reference cell circuit.
3. The method of claim 1 wherein programming the at least one of the reference cells of the first reference cell circuit to one of a plurality of predetermined states includes programming the at least one of the reference cells of the first reference cell circuit during an initialization sequence.
4. The method of claim 1 further including re-programming the at least one of the reference cells of the first reference cell circuit to a different one of the plurality of predetermined states.
5. The method of claim 4 further including re-programming the at least one of the reference cells of the second reference cell circuit to a different one of the plurality of predetermined states.
6. The method of claim 1 further including programming at least one reference cell of a third reference cell circuit to one of a plurality of predetermined states wherein the third reference cell circuit is one of the plurality of reference cell circuits.
7. The method of claim 1 wherein at least one reference cell of one of the plurality of reference cell circuits is fixed in a predetermined state.
8. A method of controlling a reference current generation circuit to generate a predetermined reference current which is used by read circuitry during a read operation to data a data state of one or more memory cells, wherein the reference current generation circuit includes (i) a plurality of reference cell circuits including a first reference cell circuit and a second reference cell circuit, each reference cell circuit including a plurality of reference cells, and (ii) a reference current driver to generate the predetermined reference current, the method comprising:
programming each reference cell of the first reference cell circuit to one of a plurality of predetermined states;
programming each reference cell of the second reference cell circuit to one of a plurality of predetermined states, wherein a majority of the reference cells of the reference cell circuits is programmed to a second state and a minority of the reference cells of the reference cell circuits is programmed to a first state; and
outputting the predetermined reference current, wherein the amount of predetermined reference current is associated with the programmed states of the reference cells of the plurality of reference cell circuits.
9. The method of claim 8 wherein programming each reference cell of the first reference cell circuit to one of a plurality of predetermined states includes storing a first charge in a body region of a transistor of each reference cell of the first reference cell circuit.
10. The method of claim 8 wherein programming each reference cell of the first reference cell circuit to one of a plurality of predetermined states includes programming each reference colt of the first reference cell circuit during an initialization sequence.
11. The method of claim 8 further including re-programming at least one of the inference cells of the first reference cell circuit to a different one of the plurality of predetermined states.
12. The method of claim 11 further including re-programming all of the reference cells of the first reference cell circuit to a different one of the plurality of predetermined states.
13. The method of claim 11 further including re-programming at least one of the reference cells of the second reference cell circuit to a different one of the plurality of predetermined states.
14. The method of claim 8 further including re-balancing a read margin by programming at least one of the reference cells of the first reference cell circuit to a different one of the plurality of predetermined states.
15. The method of claim 8 further including re-balancing a read margin by programming at least one of the reference cells of the first reference cell circuit to one of the plurality of predetermined states.
16. The method of claim 5 further including re-balancing a read margin by:
programming at least one of the reference cells of the first reference cell circuit to one of the plurality of predetermined states; and
programming at least one of the reference cells of the second reference cell circuit to one of the plurality of predetermined states.
17. The method of claim 5 further including programming at least one reference cell of a third reference cell circuit to one of a plurality of predetermined states wherein the third reference cell circuit is one of the plurality of reference cell circuits.
18. The method of claim 8 wherein at least one reference cell of one of the plurality of reference cell circuits is fixed in a predetermined state.
19. A method of generating a predetermined reference current which is used by read circuitry during a read operation to data a data state of one or more memory cells, wherein predetermined reference current is generated by a reference current generation circuit having (i) a plurality of reference cell circuits including a first reference cell circuit and a second reference cell circuit, each reference cell circuit including a plurality of reference cells, and (ii) a reference current driver, the method comprising:
storing a control word in memory circuitry;
programming one or more reference cells of the first reference cell circuit to one of a plurality of predetermined states in accordance with the control word;
programming one or more reference cells of the second reference cell circuit to one of a plurality of predetermined states in accordance with the control word, wherein a majority of the reference cells of the reference cell circuits is programmed to a second state and a minority of the reference cells of the reference cell circuits is programmed to a first state; and
outputting the predetermined reference current, wherein the amount of the predetermined reference current is associated with the programmed states of the reference cells of the plurality of reference cell circuits.
20. The method of claim 19 wherein programming the at least one of the reference cells of the first reference cell circuit to one of a plurality of predetermined states includes storing a first charge in a body region of a transistor of the at least one reference cell of the first reference cell circuit.