Techniques for providing a direct injection semiconductor memory device
View Patent ↗Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for biasing a direct injection semiconductor memory device. The method may comprise applying a first voltage potential to a first N-doped region via a bit line and applying a second voltage potential to a second N-doped region via a source line. The method may also comprise applying a third voltage potential to a word line, wherein the word line is spaced apart from and capacitively coupled to a body region that is electrically floating and disposed between the first N-doped region and the second N-doped region. The method may further comprise applying a fourth voltage potential to a P-type substrate via a carrier injection line.
1. A method for biasing a direct injection semiconductor memory device comprising the steps of:
applying a first voltage potential to a first N-doped region via a bit line;
applying a second voltage potential to a second N-doped region via a source line;
applying a third voltage potential to a word line, wherein the word line is spaced apart from and capacitively coupled to a body region that is electrically floating and disposed between the first N-doped region and the second N-doped region, wherein the first N-doped region, the body region, and the second N-doped region form a bipolar transistor; and
applying a fourth voltage potential to a P-type substrate via a carrier injection line;
wherein the bit line extends from the first N-doped region in a direction that is perpendicular to a direction of at least a portion of at least one of the source line, the word line, and the carrier injection line.
2. The method according to claim 1 , further comprising increasing the third voltage potential applied to the word line from the third voltage potential applied to the word line during a hold operation to perform a read operation.
3. The method according to claim 1 , further comprising increasing the second voltage potential applied to the source line from the second voltage potential applied to the source line during a hold operation to perform a read operation.
4. The method according to claim 1 , further comprising maintaining the second voltage potential applied to the source line during a hold operation to perform a read operation.
5. The method according to claim 1 , further comprising increasing the first voltage potential applied to the bit line from the first voltage potential applied to the bit line during a hold operation in order to reduce a disturbance during a read operation.
6. The method according to claim 1 , further comprising increasing the third voltage potential applied to the word line from the third voltage potential applied to the word line during a hold operation to perform a write logic high operation.
7. The method according to claim 1 , further comprising lowering the second voltage potential applied to the source line from the second voltage potential applied to the source line during a hold operation to perform a write logic high operation.
8. The method according to claim 7 , wherein the second voltage potential applied to the source line to perform the write logic high operation is lowered to forward bias a junction between the second N-doped region and the P-type substrate.
9. The method according to claim 1 , further comprising increasing the third voltage potential applied to the respective word line from the third voltage potential applied to the respective word line during a hold operation to perform a write logic low operation.
10. The method according to claim 1 , further comprising increasing the second voltage potential applied to the source line from the second voltage potential applied to the source line during a hold operation to perform a write logic low operation.
11. The method according to claim 1 , further comprising maintaining the second voltage potential applied to the source line during a hold operation to perform a write logic low operation.
12. The method according to claim 1 , further comprising maintaining the first voltage potential applied to the bit line during a hold operation to perform a write logic low operation.
13. The method according to claim 1 , further comprising increasing the first voltage potential applied to the bit line during a write logic low operation from the first voltage potential applied to the bit line during a hold operation to maintain a logic high stored in the memory cell.
14. The method according to claim 1 , wherein the second voltage potential applied to the source line is equal to the fourth voltage potential applied to the carrier injection line during a hold operation.
15. A direct injection semiconductor memory device comprising:
a first N-doped region coupled to a bit line;
a second N-doped region coupled to a source line;
a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first N-doped region and the second N-doped region, wherein the first N-doped region, the body region, and the second N-doped region form a bipolar transistor; and
a P-type substrate coupled to a carrier injection line;
wherein the bit line extends from the first N-doped region in a direction that is perpendicular to a direction of at least a portion of at least one of the source line, the word line, and the carrier injection line.
16. The direct injection semiconductor memory device according to claim 15 , wherein the second N-doped region and the P-type substrate form a PN junction diode.
17. The direct injection semiconductor memory device according to claim 15 , wherein the source line extends from the second N-doped region in a direction that is parallel to a direction of at least a portion of at least one of the word line and the carrier injection line.
18. The direct injection semiconductor memory device according to claim 15 , wherein the source line extends from the second N-doped region in a direction that is parallel to a direction of at least a portion of at least one of the word line and the carrier injection line.
19. A method for biasing a direct injection semiconductor memory device comprising the steps of:
applying a first voltage potential to a first P-doped region via a bit line;
applying a second voltage potential to a second P-doped region via a source line;
applying a third voltage potential to a word line, wherein the word line is spaced apart from and capacitively coupled to a body region that is electrically floating and disposed between the first P-doped region and the second P-doped region, wherein the first P-doped region, the body region, and the second P-doped region form a bipolar transistor; and
applying a fourth voltage potential to an N-type substrate via a carrier injection line;
wherein the bit line extends from the first P-doped region in a direction that is perpendicular to a direction of at least a portion of at least one of the source line, the word line, and the carrier injection line.
20. A direct injection semiconductor memory device comprising:
a first P-doped region coupled to a bit line;
a second P-doped region coupled to a source line;
a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first P-doped region and the second P-doped region, wherein the first P-doped region, the body region, and the second P-doped region form a bipolar transistor; and
a N-type substrate coupled to a carrier injection line;
wherein the bit line extends from the first P-doped region in a direction that is perpendicular to a direction of at least a portion of at least one of the source line, the word line, and the carrier injection line.