Electrically floating body memory cell and array, and method of operating or controlling same
View Patent ↗An integrated circuit having a memory cell and/or memory cell array including a plurality of memory cells (as well as techniques for reading, controlling and/or operating, the memory cell, and/or memory cell array). Each memory cell includes at least one transistor having an electrically floating body transistor and an active access element. The electrically floating body region of the transistor forms a storage area or node of the memory cell wherein an electrical charge which is representative of a data state is stored in the electrically floating body region. The active access element is coupled to the electrically floating body transistor to facilitate programming of the memory cell and to provide a relatively large amount of majority carriers to the storage area or node of the memory cell during a write operation. The memory cell and/or memory cell array of the present inventions may be incorporated in an integrated circuit device, for example, a logic device (such as, for example, a microcontroller or microprocessor) or may comprise a portion of a memory device (such as, for example, a discrete memory).
1. An integrated circuit, disposed in or on a semiconductor region or layer which resides on or above a non-conducting portion of a substrate, the integrated circuit comprising:
a semiconductor memory cell including:
a transistor including:
a first semiconductor region including impurities to provide a first conductivity type;
a second semiconductor region including impurities to provide the first conductivity type;
a body region disposed between the first semiconductor region, the second semiconductor region and the non-conducting portion of the substrate, wherein the body region is electrically floating and includes impurities to provide a second conductivity type wherein the second conductivity type is different from the first conductivity type;
a gate spaced apart from the body region; and
wherein the semiconductor memory cell stores (1) a first data state which corresponds to a first charge in the body region of the transistor of the memory cell, and (2) a second data state which corresponds to a second charge in the body region of the transistor of the memory cell; and
an active access element, electrically coupled to the transistor, including a first access line, a second access line and a control node, wherein the control node of the active access element and the second semiconductor region of the transistor are a common region.
2. The integrated circuit of claim 1 wherein the first access line is a semiconductor region including impurities to provide the second conductivity type.
3. The integrated circuit of claim 2 wherein the second access line is comprised of a metal material.
4. The integrated circuit of claim 2 wherein the second access line is comprised of a semiconductor material.
5. The integrated circuit of claim 2 wherein the second access line is comprised of a doped semiconductor material.
6. The integrated circuit of claim 1 wherein the active access element further includes a dielectric, disposed between the first access line and the second access line.
7. The integrated circuit of claim 1 wherein the integrated circuit is disposed in or on a semiconductor-on-insulator substrate.
8. The integrated circuit of claim 1 wherein the integrated circuit is disposed in or on a bulk-type substrate.
9. The integrated circuit of claim 1 wherein the first access line is a semiconductor region having a conductivity type which is different from the first conductivity type.
10. The integrated circuit of claim 9 wherein the second access line is comprised of a metal material or a semiconductor material.
11. The integrated circuit of claim 1 wherein:
an amount of charge of the first charge is greater than an amount of charge of the second charge, and
in response to first write control signals applied to the memory cell to write the first data state therein, the active access element generates a first bipolar current which substantially provides the first charge in the body region of the transistor.
12. An integrated circuit, disposed in or on a semiconductor region or layer which resides on or above a non-conducting portion of a substrate, the integrated circuit comprising:
a plurality of semiconductor memory cells arranged in a matrix of rows and columns, each semiconductor memory cell includes a transistor and an active access element, wherein the transistor is electrically coupled to the active access element, and wherein:
the transistor includes:
a first semiconductor region having impurities to provide a first conductivity type;
a second semiconductor region having impurities to provide the first conductivity type;
a body region disposed between the first semiconductor region, the second semiconductor region and the non-conducting portion of the substrate, wherein the body region is electrically floating and includes impurities to provide a second conductivity type wherein the second conductivity type is different from the first conductivity type;
a gate spaced apart from the body region: and
wherein each semiconductor memory cell stores (1) a first data state which corresponds to a first charge in the body region of the transistor of the memory cell, and (2) a second data state which corresponds to a second charge in the body region of the transistor of the memory cell; and
the active access element includes a first access line, a second access line and a control node, wherein two adjacent memory cells share an active access element.
13. The integrated circuit of claim 12 wherein the first access line is comprised of a semiconductor region including impurities to provide the second conductivity type.
14. The integrated circuit of claim 13 wherein the second access line is comprised of a metal material or a semiconductor material.
15. The integrated circuit of claim 12 wherein the control node of the active access element and the second semiconductor region of the associated transistor are a common region.
16. The integrated circuit of claim 12 wherein the active access element further includes a dielectric, disposed between the first access line and the second access line.
17. The integrated circuit of claim 12 wherein the integrated circuit is disposed in or on a semiconductor-on-insulator substrate.
18. The integrated circuit of claim 12 wherein the integrated circuit is disposed in or on a bulk-type substrate.
19. The integrated circuit of claim 12 wherein the first access line is comprised of a semiconductor region to provide conductivity type which is different from the first conductivity type.
20. The integrated circuit of claim 19 wherein the second access line is comprised of a metal material or a semiconductor material.
21. The integrated circuit of claim 12 wherein:
an amount of charge corresponding to the first charge is greater than an amount of charge corresponding to the second charge, and
in response to first write control signals applied to a selected memory cell of the plurality of memory cells, the active access element of the selected memory cell generates a first bipolar current which substantially provides the first charge in the body region of the transistor of the selected memory cell.
22. An integrated circuit device comprising:
a memory cell array including a:
plurality of word lines;
plurality of bit lines;
a plurality of first access lines;
a plurality of second access lines; and
a plurality of semiconductor memory cells arranged in a matrix of rows and columns, each semiconductor memory cell includes a transistor and an active access element, wherein the transistor is electrically coupled to the active access element, and wherein:
the transistor includes:
a first semiconductor region, electrically coupled to an associated bit line, having impurities to provide a first conductivity type;
a second semiconductor region having impurities to provide the first conductivity type;
a body region disposed between the first semiconductor region, the second semiconductor region and a non-conducting portion of the substrate, wherein the body region is electrically floating and includes impurities to provide a second conductivity type wherein the second conductivity type is different from the first conductivity type;
a gate, which is electrically coupled to an associated word line and spaced apart from the body region; and
wherein each semiconductor memory cell stores (1) a first data state which corresponds to a first charge in the body region of the transistor of the memory cell, and (2) a second data state which corresponds to a second charge in the body region of the transistor of the memory cell; and
the active access element includes a first access region electrically coupled to an associated first access line, a second access region electrically coupled to an associated second access line, and a control node.
23. The integrated circuit of claim 22 wherein the first access region is a semiconductor region including impurities to provide the second conductivity type.
24. The integrated circuit of claim 23 wherein the second access region is comprised of a metal material or a semiconductor material.
25. The integrated circuit of claim 22 wherein the control node of the active access element and the second semiconductor region of the associated transistor are a common region.
26. The integrated circuit of claim 22 wherein two adjacent memory cells share an active access element.
27. The integrated circuit of claim 22 wherein two adjacent memory cells share at least a portion of the first access region of the associated active access element.
28. The integrated circuit of claim 27 wherein the first semiconductor region of the transistors of the two adjacent memory cells are connected to the same bit line.
29. The integrated circuit of claim 22 wherein the active access element further includes a dielectric, disposed between the first access region and the second access region.
30. The integrated circuit of claim 22 wherein the integrated circuit is disposed (i) in or on a semiconductor-on-insulator substrate or (ii) in or on a bulk-type substrate.
31. The integrated circuit of claim 22 wherein the first access region is a semiconductor region having a conductivity type which is different from the first conductivity type.
32. The integrated circuit of claim 31 wherein the second access region is comprised of a metal material or a semiconductor material.
33. The integrated circuit of claim 22 wherein:
an amount of charge corresponding to the first charge is greater than an amount of charge corresponding to the second charge, and
in response to first write control signals applied to a selected memory cell of the plurality of memory cells, the active access element of the selected memory cell generates a first bipolar current which substantially provides the first charge in the body region of the transistor of the selected memory cell.
34. An integrated circuit, disposed in or on a semiconductor region or layer which resides on or above a non-conducting portion of a substrate, the integrated circuit comprising:
a plurality of semiconductor memory cells arranged in a matrix of rows and columns, each semiconductor memory cell includes a transistor and an active access element, wherein the transistor is electrically coupled to the active access element, and wherein:
the transistor includes:
a first semiconductor region having impurities to provide a first conductivity type;
a second semiconductor region having impurities to provide the first conductivity type;
a body region disposed between the first semiconductor region, the second semiconductor region and the non-conducting portion of the substrate, wherein the body region is electrically floating and includes impurities to provide a second conductivity type wherein the second conductivity type is different from the first conductivity type;
a gate spaced apart from the body region; and
wherein each semiconductor memory cell stores (1) a first data state which corresponds to a first charge in the body region of the transistor of the memory cell, and (2) a second data state which corresponds to a second charge in the body region of the transistor of the memory cell; and
the active access element includes a first access line, a second access line and a control node, wherein two adjacent memory cells share at least a portion of the first access line of the associated active access element.
35. The integrated circuit of claim 34 wherein:
an amount of charge corresponding to the first charge is greater than an amount of charge corresponding to the second charge, and
in response to first write control signals applied to a selected memory cell of the plurality of memory cells, the active access element of the selected memory cell generates a first bipolar current which substantially provides the first charge In the body region of the transistor of the selected memory cell.