Semiconductor memory device
View Patent ↗A semiconductor memory device is disclosed. In one particular exemplary embodiment, the semiconductor memory device includes a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region connected to a source line extending in a first orientation. Each memory cell may also include a second region connected to a bit line extending a second orientation. Each memory cell may further include a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The semiconductor device may also include a first barrier wall extending in the first orientation and a second barrier wall extending in the second orientation and intersecting with the first barrier wall to form a trench region configured to accommodate each of the plurality of memory cells.
1. A semiconductor memory device comprising:
a plurality of memory cells arranged in an array of rows and columns, each memory cell having:
a first region electrically connected to a source line;
a second region electrically connected to a bit line; and
a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region;
a first barrier wall continuously extending in a first orientation of the array directly adjacent to a first side of the first region of the plurality of memory cells; and
a second barrier wall extending in a second orientation of the array directly adjacent to a second side of the first region of the plurality of memory cells; wherein the second barrier wall intersects with the first barrier wall to form a trench region configured to accommodate each of the plurality of memory cells;
wherein the bit line is electrically connected to respective second regions of immediately adjacent memory cells.
2. The semiconductor memory device according to claim 1 , wherein the first region and the second region are N-doped regions.
3. The semiconductor memory device according to claim 2 , wherein the body region is an P-doped region.
4. The semiconductor memory device according to claim 2 , wherein the body region is an undoped region.
5. The semiconductor memory device according to claim 1 , wherein the first barrier wall and the second barrier wall are formed of an insulating oxide material.
6. The semiconductor memory device according to claim 1 , wherein the first barrier wall and the second barrier wall are formed on a P-type substrate.
7. The semiconductor memory device according to claim 1 , wherein the word line is disposed along a side of the body region.
8. The semiconductor memory device according to claim 1 , wherein a height of the word line is similar to a height of the body region.
9. The semiconductor memory device according to claim 1 , wherein the word line is disposed adjacent to a side of the body region and at least a portion of a side of the first region.
10. The semiconductor memory device according to claim 1 , wherein the word line is disposed along a side of the body region and at least a portion of a side of the second region.
11. The semiconductor memory device according to claim 1 , wherein the word line is disposed along a side of the body region, at least a portion of a side of the first region, and at least a portion of a side of the second region.
12. The semiconductor memory device according to claim 1 , wherein a height of the word line is shorter than a height of the body region.
13. The semiconductor memory device according to claim 1 , wherein the word line has a rectangular cross-sectional shape.
14. The semiconductor memory device according to claim 1 , wherein the word line has a U cross-sectional shape.
15. The semiconductor memory device according to claim 1 , wherein the word line has an L cross-sectional shape.
16. The semiconductor memory device according to claim 1 , wherein the word line is capacitively coupled to a plurality of the body regions.
17. The semiconductor memory device according to claim 1 , wherein the word line is coupled to a constant voltage potential.
18. The semiconductor memory device according to claim 1 , wherein the word line is coupled to a ground voltage potential.
19. The semiconductor memory device according to claim 1 , wherein the array of memory cells comprises a dummy row of memory cells separating adjacent rows of the memory cells.
20. The semiconductor memory device according to claim 19 , wherein the bit line is connected to the second region via a bit line contact.
21. The semiconductor memory device according to claim 1 , wherein the source line extends in the first orientation configured in a plane below the first region.
22. The semiconductor memory device according to claim 1 , wherein the bit line extends in the second orientation configured in a plane above the second region.