Semiconductor memory device including a double-gate dynamic random access memory cell having reduced current leakage
View Patent ↗A dynamic random access memory (DRAM) cell and associated array are disclosed. The DRAM cell ( 300 ) includes a storage capacitor ( 304 ) and a pass transistor ( 302 ). The pass transistor ( 302 ) includes a source region ( 322 ), drain region ( 320 ) and channel region ( 324 ). A top gate ( 318 ) is disposed over the channel region ( 324 ) and a bottom gate ( 310 ) is disposed below the channel region ( 324 ). The top gate ( 318 ) and bottom gate ( 310 ) are commonly driven to provide greater control of the pass transistor ( 302 ) operation, including an off state with reduced source-to-drain leakage. The DRAM array ( 400 ) includes memory cells ( 414 ) having pass transistors ( 500 ) with double-gate structures. Memory cells ( 414 ) within the same row are commonly coupled to a top word line and bottom word line. The resistance of the top and bottom word lines is reduced by a word line strap layer ( 600 ). The DRAM array ( 400 ) further includes a strapping area that is void of memory cells. Conductive contact between the top word line, bottom word line, and word line strap layer ( 600 ) of each row is made within the strapping area by way of strapping vias ( 604 ) and top-to-bottom word line vias ( 602 ).
1. A semiconductor memory device, comprising:
a dynamic random access memory cell requiring a data refresh including
a transistor having a first gate and a second gate disposed on opposite sides of a channel region; and
the first gate is separated from the channel region by a first insulating layer and the second gate is separated from the channel region by a second insulating layer.
2. The semiconductor memory device of claim 1 , wherein:
the first gate is coupled to a first word line.
3. The semiconductor memory device of claim 2 , wherein:
the second gate is coupled to a second word line.
4. The semiconductor memory device of claim 3 , wherein:
the first word line is coupled to a word line driver.
5. The semiconductor memory device of claim 4 , wherein:
the second gate is formed between a substrate and the channel region.
6. The semiconductor memory device of claim 2 , wherein:
the first word line is coupled to a word line driver.
7. The semiconductor memory device of claim 6 , wherein:
the second gate is formed between a substrate and the channel region.
8. The semiconductor memory device of claim 1 , wherein:
the second gate is formed between a substrate and the channel region; and
the first gate is doped with a conductivity type.
9. The semiconductor memory device of claim 1 , wherein:
the second gate is formed between a substrate and the channel region; and
the second gate is doped with a conductivity type.
10. The semiconductor memory device of claim 1 , wherein:
the data refresh is required within a predetermined pause period.
11. A semiconductor memory device, comprising:
a dynamic random access memory cell requiring a data restore including
a transistor having a first gate and a second gate disposed on opposite sides of a channel region; and
the first gate is separated from the channel region by a first insulating layer and the second gate is separated from the channel region by a second insulating layer.
12. The semiconductor memory device of claim 11 , wherein:
the first gate is coupled to a first word line.
13. The semiconductor memory device of claim 12 , wherein:
the second gate is coupled to a second word line.
14. The semiconductor memory device of claim 13 , wherein:
the first word line is coupled to a word line driver.
15. The semiconductor memory device of claim 14 , wherein:
the second gate is formed between a substrate and the channel region.
16. The semiconductor memory device of claim 12 , wherein:
the first word line is coupled to a word line driver.
17. The semiconductor memory device of claim 16 , wherein:
the second gate is formed between a substrate and the channel region.
18. The semiconductor memory device of claim 11 , wherein:
the second gate is formed between a substrate and the channel region; and
the first gate is doped with a conductivity type.
19. The semiconductor memory device of claim 11 , wherein:
the second gate is formed between a substrate and the channel region; and
the second gate is doped with a conductivity type.
20. The semiconductor memory device of claim 11 , wherein:
the data restore is required within a read operation.