Reference buffer with dynamic current control
View Patent ↗A method can allow a system to selectively control increasing of a bias source in a reference buffer or decreasing impedance looking into a output of the reference buffer for a temporary or selective time period, which can result in an increased overall efficiency of the system. The method can include at least the following steps. A first input signal is received at an input of a reference buffer. A second input signal is received from a load at an output of the reference buffer. A value of a bias source coupled to the output of the reference buffer is modulated, such that a spike of a signal at the output of the reference buffer caused by the second input signal is maintained below a threshold value. Alternatively, an impedance looking into the output of the reference buffer is modulated, such that a spike of a signal at the output of the reference buffer caused by the second input signal is maintained below a threshold value.
1. A method comprising:
(a) receiving a first input signal at an input of a reference buffer;
(b) receiving a second input signal from a load at an output of the reference buffer; and
(c) modulating a value of a bias source coupled to the output of the reference buffer, such that a spike of a value at the output of the reference buffer caused by step (b) is maintained below a threshold value;
wherein the second input signal varies during first and second phases of operation of the load; and the modulating step begin during one of the first and second phases and ends during another one of the first and second phases.
2. The method of claim 1 , wherein the load comprises a temporally varying load.
3. The method of claim 1 , wherein the load comprises a switched capacitor load.
4. The method of claim 1 , wherein step (c) comprises temporarily increasing the value of the bias source.
5. The method of claim 1 , wherein step (a) comprises using one of a constant single-ended input signal and a constant differential input signal as the first input signal.
6. The method of claim 1 , further comprising positioning the bias source within the reference buffer.
7. A method comprising:
(a) receiving a first input signal at an input of a reference buffer;
(b) receiving a second input signal from a load at an output of the reference buffer; and
(c) modulating an impedance looking into the output of the reference buffer, such that a spike of a value at the output of the reference buffer caused by step (b) is maintained below a threshold value;
wherein the second input signal varies during first and second phases of operation of the load; and the modulating step begin during one of the first and second phases and ends during another one of the first and second phases.
8. The method of claim 7 , wherein the load comprises a temporally varying load.
9. The method of claim 7 , wherein the load comprises a switched capacitor load.
10. The method of claim 7 , wherein step (c) comprises modulating a value of a bias source coupled to the output.
11. The method of claim 7 , wherein step (c) comprises temporarily decreasing a value of the impedance.
12. The method of claim 7 , wherein step (c) comprises temporarily increasing a value of a bias source coupled to the output.
13. The method of claim 7 , wherein the load comprises a temporally varying load or a switched capacitor load.
14. The method of claim 7 , wherein step (a) comprises using one of a constant single-ended input signal and a constant differential input signal.
15. A system comprising:
a reference buffer having an input and an output;
a bias source coupled to the output;
a control device coupled to the bias source; and
a load coupled to the output,
wherein receiving charge from the load at the output causes a spike at the output and wherein the control device modulates the bias source so that the spike is maintained below a threshold value;
wherein the receiving charge varies during first and second phases of operation of the load; and the modulating begin during one of the first and second phases and ends during another one of the first and second phases.
16. The system of claim 15 , wherein the bias source is a current source.
17. The system of claim 15 , wherein the control device is a register.
18. The system of claim 15 , wherein the bias source is positioned within the reference buffer.