IP Library Granted Patent US 7,088,129
Granted Patent B2
US 7,088,129 · App. 10/835,906 · Granted Aug 8, 2006

Hybrid binary/thermometer code for controlled-voltage integrated circuit output drivers

Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
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Quick Facts
Patent No.
US 7,088,129
App. No.
10/835,906
Granted
Aug 8, 2006
Kind
B2
Abstract

A hybrid binary/thermometer code is employed to adjust the output impedance of a variable impedance output driver circuit having an impedance network comprising a plurality of impedance legs each programmably electrically connectable according to the hybrid binary/thermometer code in parallel between a voltage source and the signal pad. The plurality of impedance legs are partitioned into one or more set pairs of binary stepped impedance legs and corresponding thermometer stepped impedance legs. A binary set of calibration signals in the hybrid binary/thermometer code steps a given set of binary stepped impedance legs according to a binary code and a thermometer set of calibration signals in the hybrid binary/thermometer code steps the corresponding set of thermometer stepped impedance legs according to a thermometer code once per full count iteration of the binary set of calibration signals.

Claims (44)

1. A variable impedance network for variably adjusting the output impedance of a node of a circuit, comprising:

one or more impedance legs electrically connected between a voltage source and said node;

a first set of switchable impedance legs programmably electrically connectable between said voltage source and said node by a first set of calibration signals each of which corresponds to a respective one or more of said switchable impedance legs in said first set of switchable impedance legs;

a second set of switchable impedance legs programmably electrically connectable between said voltage source and said node by a second set of calibration signals each of which corresponds to a respective one or more of said switchable impedance legs in said second set of switchable impedance legs; and

a controller which generates said first set of calibration signals and said second set of calibration signals, wherein said controller steps said first set of calibration signals according to a binary code and steps said second set of calibration signals according to a thermometer code once per full count iteration of said first set of calibration signals.

2. A variable impedance network in accordance with claim 1 , wherein:

said first set of calibration signals and said second set of calibration signals represent bits with respective predetermined bit positions in a calibration word, and wherein each of said first set of switchable impedance legs is weighted increasingly in order of the respective predetermined bit position of its corresponding calibration signal in the calibration word.

3. A variable impedance network in accordance with claim 2 , wherein:

each of said first set of switchable impedance legs is binary weighted according to the bit position of its corresponding calibration signal in the calibration word.

4. A variable impedance network in accordance with claim 1 , wherein:

each of said switchable impedance legs in said first set of impedance legs and said second set of impedance legs comprises a field effect transistor (FETs) sized to have a corresponding predetermined respective impedance.

5. A variable impedance network in accordance with claim 1 , further comprising:

a third set of switchable impedance legs programmably electrically connectable between said voltage source and said node by a third set of calibration signals each of which corresponds to a respective one or more of said switchable impedance legs in said third set of switchable impedance legs;

a fourth set of switchable impedance legs programmably electrically connectable between said voltage source and said node by a fourth set of calibration signals each of which corresponds to a respective one or more of said switchable impedance legs in said fourth set of switchable impedance legs; and

wherein said controller generates said third set of calibration signals and said fourth set of calibration signals, wherein said controller steps said first set of calibration signals and said third set of calibration signals, taken as a combination, according to a binary code and steps said fourth set of calibration signals according to a thermometer code once per full count iteration of said combination of said first set of calibration signals end said third set of calibration signals.

6. A variable impedance network in accordance with claim 5 , wherein:

said first set of calibration signals, said second set of calibration signals, said third set of calibration signals, and said fourth set of calibration signals represent bits with respective predetermined bit positions in a calibration word, and wherein each of said first set of switchable impedance legs and each of said third set of switchable impedance legs is weighted increasingly in order of the bit position of its corresponding calibration signal in the calibration word.

7. A variable impedance network in accordance with claim 5 , wherein:

each of said first set of switchable impedance legs and each of said third set of switchable impedance legs is binary weighted according to the bit position of its corresponding calibration signal in the calibration word.

8. A variable impedance network in accordance with claim 5 , wherein:

each of said switchable impedance legs in said first set of impedance legs, said second set of impedance legs, said third set of impedance legs, and said fourth set of impedance legs comprises a field effect transistor (FETs) sized to have a corresponding predetermined respective impedance.

9. A method for variably adjusting the output impedance of a node of a circuit, said circuit comprising an impedance network interposed between a voltage source and said node, said impedance network comprising one or more impedance legs electrically connected between said voltage source and said node, a first set of switchable impedance legs programmably electrically connectable between said voltage source and said node by a first set of calibration signals each of which corresponds to a respective one or more of said switchable impedance legs in said first set of switchable impedance legs, and a second set of switchable impedance legs programmably electrically connectable between said voltage source and said node by a second set of calibration signals each of which corresponds to a respective one or more of said switchable impedance legs in said second set of switchable impedance legs, said method comprising the steps of:

stepping said first set of calibration signals according to a binary code; and

stepping said second set of calibration signals according to a thermometer code once per full count iteration of said first set of calibration signals.

10. A method in accordance with claim 9 , wherein said first set of calibration signals and said second set of calibration signals represent bits with respective predetermined bit positions in a calibration word, said method further comprising:

weighting each of said first set of switchable impedance legs increasingly in order of the respective predetermined bit position of its corresponding calibration signal in the calibration word.

11. A method in accordance with claim 9 , wherein said first set of calibration signals and said second set of calibration signals represent bits with respective predetermined bit positions in a calibration word, said method further comprising:

weighting each of said first set of switchable impedance legs according to a binary weighting scheme in order of the bit position of its corresponding calibration signal in the calibration word.

12. A method in accordance with claim 9 , wherein said impedance network further comprises a third set of switchable impedance legs programmably electrically connectable between said voltage source and said node by a third set of calibration signals each of which corresponds to a respective one or more of said switchable impedance legs in said third set of switchable impedance legs, and a fourth set of switchable impedance legs programmably electrically connectable between said voltage source and said node by a fourth set of calibration signals each of which corresponds to a respective one or more of said switchable impedance legs in said fourth set of switchable impedance legs, said method further comprising the steps of:

stepping said first set of calibration signals and said third set of calibration signals, taken as a combination, according to a binary code; and

stepping said fourth set of calibration signals according to a thermometer code once per full count iteration of said combination of said first set of calibration signals and said third set of calibration signals.

13. A method in accordance with claim 12 , said method further comprising:

weighting each of said first set of switchable impedance legs and said third set of impedance legs increasingly in order of the respective predetermined bit position of its corresponding calibration signal in the calibration word.

14. A method in accordance with claim 13 , said method further comprising

weighting each of said first set of switchable impedance legs according to a binary weighting scheme in order of the bit position of its corresponding calibration signal in the calibration word.

15. A variable impedance network for variably adjusting the output impedance of a node of a circuit, comprising:

one or more impedance legs electrically connected between a voltage source and said node;

a first set of switchable impedance legs programmably electrically connectable between said voltage source and said node by a first set of calibration signals each of which corresponds to a respective one or more of said switchable impedance legs in said first set of switchable impedance legs;

a second set of switchable impedance legs programmably electrically connectable between said voltage source and said node by a second set of calibration signals each of which corresponds to a respective one or more of said switchable impedance legs in said second set of switchable impedance legs;

a third set of switchable impedance legs programmably electrically connectable between said voltage source and said node by a third set of calibration signals each of which corresponds to a respective one or more of said switchable impedance legs in said third set of switchable impedance legs;

a fourth set of switchable impedance legs programmably electrically connectable between said voltage source and said node by a fourth set of calibration signals each of which corresponds to a respective one or more of said switchable impedance legs in said fourth set of switchable impedance legs;

wherein said first set of calibration signals, said second set of calibration signals, said third set of calibration signals, and said fourth set of calibration signals represent bits with different respective predetermined bit positions in a calibration word, and wherein each of said first set of switchable impedance legs and each of said third set of switchable impedance legs is binary weighted according to the bit position of its corresponding calibration signal in the calibration word; and

a controller which generates said first set of calibration signals, said second set of calibration signals, said third set of calibration signals, and said fourth set of calibration signals;

wherein said controller steps said first set of calibration signals according to a binary code and steps said second set of calibration signals according to a thermometer code once per full count iteration of said first set of calibration signals, and steps said first set of calibration signals and said third set of calibration signals, taken as a combination, according to a binary code and steps said fourth set of calibration signals according to a thermometer code once per full count iteration of said combination of said first set of calibration signals and said third set of calibration signals.

Assignments (11)
MERGER Recorded Mar 3, 2023
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; BROADCOM INTERNATIONAL PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 062952/0850 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2020
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
To: BROADCOM INTERNATIONAL PTE. LTD.
Reel/Frame 053771/0901 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0097. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048555/0510 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0097 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 017206 FRAME: 0666. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 6, 2016
From: AGILENT TECHNOLOGIES, INC.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 038632/0662 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032851-0001) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 037689/0001 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032851/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2006
From: AGILENT TECHNOLOGIES, INC.
To: AVAGO TECHNOLOGIES GENERAL IP PTE. LTD.
Reel/Frame 017206/0666 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 13, 2004
From: HUMPHREY, GUY HARLAN; LINAM, DAVID LAWRENCE
To: AGILENT TECHNOLOGIES, INC.
Reel/Frame 014844/0464 →
Continuity (1)
Related Publication 20050242830A1 · Nov 3, 2005